A High‐Performance RSA Coprocessor Based on Half‐Carry‐Save and Dual‐Core MAC Architecture

Ding, Yanyu; Hu, Jianxun; Wang, Biao; Tan, Hongzhou

doi:10.1049/cje.2017.11.013

Cited by 4 publications

(1 citation statement)

References 14 publications

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“…Ref. [22] introduces the half-carry-save form to reduce the bit width of the operand in the CPA, thereby reducing the delay of the critical path. However, it still has the problem of a long carry chain compared with the redundant number system, so it cannot achieve a good performance in a lower area.…”

Section: Results and Comparisonsmentioning

confidence: 99%

A Scalable Montgomery Modular Multiplication Architecture with Low Area-Time Product Based on Redundant Binary Representation

Zhaoji

Zhang

2022

Electronics

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The Montgomery modular multiplication is an integral operation unit in the public key cryptographic algorithm system. Previous work achieved good performance at low input widths by combining Redundant Binary Representation (RBR) with Montgomery modular multiplication, but it is difficult to strike a good balance between area and time as input bit widths increase. To solve this problem, based on the redundant Montgomery modular multiplication, in this paper, we propose a flexible and pipeline hardware implementation of the Montgomery modular multiplication. Our proposed structure guarantees a single-cycle delay between two-stage pipeline units and reduces the length of the critical path by redistributing the data paths between the pipelines and preprocessing the input in the loop. By analyzing the structure and comparing the related work in this paper, our structure ensures a lower area-time product while achieving a controllable and small area consumption. The comprehensive results under different Taiwan Semiconductor Manufacturing Company (TSMC) processes demonstrate the advantages of our structure in terms of flexibility and area-time product.

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Section: Results and Comparisonsmentioning

confidence: 99%