A high-performance triple patterning layout decomposer with balanced density

Abstract

Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high performance layout decomposer for TPL. Density balancing is seamlessly integrated into all key steps in our TPL layout decomposition, including density-balanced semi-definite programming (SDP), density-based mapping, and densitybalanced graph simplification. Our new TPL decomposer can obtain high performance even compared to previous state-of-the-art layout decomposers which are not balanced-density aware, e.g., by Yu et al. (ICCAD'11), Fang et al. (DAC'12), and Kuang et al. (DAC'13). Furthermore, the balanced-density version of our decomposer can provide more balanced density which leads to less edge placement error (EPE), while the conflict and stitch numbers are still very comparable to our non-balanced-density baseline.

Discrete Relaxation Method for Triple Patterning Lithography Layout Decomposition

“…The TPL layout decomposition problem and the problem with balanced density are NP-complete, which were proved by Yu et al [10], [11]. Hence most of algorithms for the TPL layout decomposition problem belong to heuristic methods.…”

“…The second approach is the semidefinite program relaxations of the TPL layout decomposition problem by Yu et al [10], [11], which are continuous relaxations. In [10], Yu et al formulated the TPL problem as a linear binary program and a vector program.…”

Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography

“…LELELE type TPL technology [8][9][10][11][12][13][14][15][16][17][18] in which litho-etch process is repeated three times is often discussed in literature. However, it suffers from native conflict and overlay problems.…”

“…Triple patterning lithography (TPL) is one of the most promising techniques in the 14 nm logic node and beyond. In order to realize a target pattern, various types of techniques including design for manufacturability, such as LELE type double patterning lithograph [1][2][3][4][5][6][7], LELELE type TPL [8][9][10][11][12][13][14][15][16][17][18], LELECUT type TPL [19], and side wall process [20], are used in addition to a basic litho-etch process with optimized mask. These techniques are summarized in [21,22].…”

Toward Unidirectional Routing Closure in Advanced Technology Nodes

“…In general, there exist two types of MPL, Litho-Etch-Litho-Etch (LELE) type and self-aligned type. LELE-type of MPL allows stitch insertions and two-dimensional patterns [27], [59], [70], [71], [77], but coloring and overlay compensation schemes become extremely complicated for triple patterning lithography and beyond [12], [15], [30], [38], [60], [73], [76], [81]. Self-aligned type of MPL can minimize electrical variations from overlay and line-edge-roughness but introduces complex coloring and line-end constraints [40], [42], [56].…”