GaAs IC Symposium Technical Digest 1992
DOI: 10.1109/gaas.1992.247205
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A high power-added efficiency GaAs power MESFET operating at a very low drain bias for use in L-band medium-power amplifiers

Abstract: A power MESFET offering a high qadd operating at a very low VDD has been developed. MESFET has a buried p-layer and o u r improved LDD n+ self-aligned structure which include highly electrically activated ion-implanted regions due to rapid thermalcap annealing using double-layered SiN films deposited by ECR plasma CVD. The device geometries and implantation conditions were optimized s o as to achieve a high V(BR)cDo of more than 10 V and a low VI( of less than 0.5 V, and s o as to minimize the bias dependence … Show more

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Cited by 15 publications
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“…Figure 7 shows a photograph of an IC chip that we have manufactured. The MESFETs used are planar-type MESFETs (with no recess) [5], and have gate lengths of 0.7 , U m. The gate widths are 1400 p m for MESFETI and MESFET3, and 400 p m for MESFET2 and MESFET4. The pull-up capacitance is 10 pF (Ca + Cb), and the resistance applied to each gate is 7 k fl .…”
Section: Low Insertion Loss I High Isolationmentioning
confidence: 99%
“…Figure 7 shows a photograph of an IC chip that we have manufactured. The MESFETs used are planar-type MESFETs (with no recess) [5], and have gate lengths of 0.7 , U m. The gate widths are 1400 p m for MESFETI and MESFET3, and 400 p m for MESFET2 and MESFET4. The pull-up capacitance is 10 pF (Ca + Cb), and the resistance applied to each gate is 7 k fl .…”
Section: Low Insertion Loss I High Isolationmentioning
confidence: 99%