A high‐resolution all‐digital pulse‐width modulator architecture with a tunable delay element in CMOS

Morales, Juan I.; Chierchie, Fernando; Mandolesi, Pablo S.; Paolini, Eduardo E.

doi:10.1002/cta.2803

Cited by 7 publications

(8 citation statements)

References 33 publications

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“…The problem with this method is that the addition of new transistors will lead to larger size circuits and can introduce more noise to the circuit. Others have used time-delay elements to correct the mismatch in the time delay on a chip [13,14]. Nevertheless, creating delay elements can be a challenging task due to their extensive design specifications and various trade-offs involved.…”

Section: Introductionmentioning

confidence: 99%

A Mayfly-Based Approach for CMOS Inverter Design with Symmetrical Switching

2023

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This paper presents a novel approach to designing a CMOS inverter using the Mayfly Optimization Algorithm (MA). The MA is utilized in this paper to obtain symmetrical switching of the inverter, which is crucial in many digital electronic circuits. The MA method is found to have a fast convergence rate compared to other optimization methods, such as the Symbiotic Organisms Search (SOS), Particle Swarm Optimization (PSO), and Differential Evolution (DE). A total of eight different sets of design parameters and criteria were analyzed in Case I, and the results confirmed compatibility between the MA and Spice techniques. The maximum discrepancy in fall time across all design sets was found to be 2.075711 ns. In Case II, the objective was to create a symmetrical inverter with identical fall and rise times. The difference in fall and rise times was minimized based on Spice simulations, with the maximum difference measuring 0.9784731 ns. In Case III, the CMOS inverter was designed to achieve symmetrical fall and rise times as well as propagation delays. The Spice simulation results demonstrated that symmetry had been successfully achieved, with the minimum difference measuring 0.312893 ns and the maximum difference measuring 1.076540 ns. These Spice simulation results are consistent with the MA results. The results conclude that the MA is a reliable and simple optimization technique and can be used in similar electronic topologies.

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Section: Introductionmentioning

confidence: 99%

A Mayfly-Based Approach for CMOS Inverter Design with Symmetrical Switching

2023

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“…However, the pulse width resolution was limited to the period of the counting clock [17]. Morales J. I. et al proposed a pulse generating circuit based on a digitally controlled delay element to achieve a variable time interval of up to 54 ps [18].…”

Section: Introductionmentioning

confidence: 99%

Metrology and Measurement Systems

Liu,

Fu,

Kong

et al. 2021

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Adjustable-width pulse signals are widely used in systems such as test equipment for hold time, response time and radar testing. In this study, we proposed a pulse generation method based on virtual sampling with ultra-high pulse width resolution. In the proposed method, the sampling rate of a digital-to-analogue converter (DAC) was adjusted to considerably improve pulse width resolution. First, the sampling rate was matched with the target pulse width resolution to digitally sample the ideal signal and generate digital waveform sampling points. Next, the signal bandwidth of the DAC was matched using a low-pass digital filter. Finally, the waveform sampling points were downsampled using an integer factor and output after digital-to-analogue conversion. The waveform pulse width information generated by high-frequency digital sampling was passed step by step and retained in the final output analogue signal. A DAC with a sampling rate of 1.25 GSa/s was used, and the pulse width resolution of the pulse signal was 0.1 ns. Theoretically, a sampling rate of 10 GSa/s is required to achieve 0.1 ns resolution. This method is simple, has a low cost, and exhibits excellent performance.

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“…Therefore, digital pulse‐width modulators (DPWMs) are being used more and more widely. For example, DPWMs are used in the high‐resolution dimming of light‐emitting diode (LED) lighting to avoid flicker phenomenon, 1,2 motor control applications, 3 RF modulators based on switching amplifiers, 4 switching audio amplifiers to achieve high fidelity with low distortion, 5 and digitally controlled switched‐mode power suppliers 6,7 . Among these applications, digitally controlled switching power supplies are most widely used for high‐precision DPWM.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of a hybrid DPWM under 50 ps resolution based on general‐purpose FPGA

Zhang

et al. 2020

Circuit Theory & Apps

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SummaryHigh‐resolution pulse width modulators are used widely in different fields of electrical engineering, such as dimming of light‐emitting diode (LED) lighting, motor control, RF modulators, audio amplifiers, and switch‐mode power supplies. To realize a high‐resolution digital pulse‐width modulator (DPWM) in a limited inner system clock, a simple implementation of a hybrid DPWM with the resolution under 50 ps based on a general‐purpose field‐programmable gate array (FPGA) is described. The multiplexer device implementing the fast carry‐chain path and an AND gate controlling the selection input are used as a delay unit. The manual routing or placement is not required in the proposed approach, which just needs some conditional constraints. Some different conditional constraints influencing the monotonicity and resolution of DPWM are discussed. Finally, a 1 MHz switching frequency DPWM with 40 ps resolution is experimentally demonstrated, with high monotonicity and linearity. Further, a synchronous buck with and without this high‐resolution DPWM is experimentally compared to illustrate the regulation resolution.

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A high‐resolution all‐digital pulse‐width modulator architecture with a tunable delay element in CMOS

Cited by 7 publications

References 33 publications

A Mayfly-Based Approach for CMOS Inverter Design with Symmetrical Switching

A Mayfly-Based Approach for CMOS Inverter Design with Symmetrical Switching

Metrology and Measurement Systems

Design and implementation of a hybrid DPWM under 50 ps resolution based on general‐purpose FPGA

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