A High-Resolution Digital Phase Interpolator Based CDR with a Half-Rate Hybrid Phase Detector

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

“…To perform high-resolution phase generation, we employed an analog, inverter-based PI based on previous works [42][43][44][45][47][48][49][50][51][52][53][54] in the proposed BBCDR. Despite its intrinsic phase capture range limitation, this topology is preferable to digital PIs [42][43][44]48,49 for its intrinsic simplicity, adjustable output phase, and low power.…”

“…It follows that the PI has an intrinsic phase capture range limitation and cannot provide 0 to 360 phase rotation. 43 We choose this open-loop PI structure instead of a close-loop PI-based DLL 42 with the consideration that the external tunning of supply voltage is suitable to cover the phase error caused by PVT variation. Since we found that a small change in the supply voltage will result in a sufficiently large phase variation to cover the phase tuning requirement, this PI will not result in a large variation in output signal amplitude while tuning the phase.…”

“…Moreover, the analog PI requires a reset logic to limit the control voltage within the range. It follows that the PI has an intrinsic phase capture range limitation and cannot provide 0 to 360° phase rotation 43 …”

“…An alternative solution consists in adopting a current-starved RO used to generate a quadrature clock and then obtaining an eight-phase clock signal by interpolation, as in Figure 1C. [42][43][44][45] Compared to Figure 1A, the adoption of a four-phase RO greatly reduces power consumption, leading to better energy efficiency. Besides, when compared with the scheme in Figure 1B, both the four-phase RO and eight-phase clocks are at the same frequency f CK , which avoids the burden of a very high-frequency oscillator.…”

“…Finally, with the divider operating in an open loop, it does not precisely constrain the phase relationship of the generated clock signals. An alternative solution consists in adopting a current‐starved RO used to generate a quadrature clock and then obtaining an eight‐phase clock signal by interpolation, as in Figure 1C 42–45 . Compared to Figure 1A, the adoption of a four‐phase RO greatly reduces power consumption, leading to better energy efficiency.…”