A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA

Yan, Chenggang; Hu, Chen; Wu, Jing

doi:10.3390/app9132705

Cited by 8 publications

(3 citation statements)

References 14 publications

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“…On the contrary, the relative time generators and comparators are robust to PVT. However, the relative methods are hampered by path or element mismatches [36].…”

Section: Temperature Influencementioning

confidence: 99%

Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA

Wojciechowski,

Marcinek,

Pleskacz

2023

Electronics

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Phase jitter is one of the crucial factors in modern digital electronics, determining the reliability of a design. This paper presents a novel approach to designing a jitter comparison system and methodology for FPGA chips using a Tapped Delay Line (TDL)—commonly used to implement a Time-to-Digital Converter (TDC). The design and its revision utilizing latches replacing some of the flip-flops are presented and discussed, with potential further improvements. A minimal temperature influence is verified and presented. The methodology of automated relative jitter measurements is discussed. Multiple different FPGA clock signal path configurations are measured, and the results are presented. The influence of clock routing is identified as critical when MMCM or PLL modules are omitted. It is demonstrated that with careful resource and routing allocation, the clock signal’s jitter performance does not have to be deteriorated by the absence of jitter filtering blocks. The proposed technique was implemented and verified and relative jitter performance was measured in the AMD/Xilinx Artix 7 35T FPGA platform.

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“…On the contrary, the relative time generators and comparators are robust to PVT. However, the relative methods are hampered by path or element mismatches [36].…”

Section: Temperature Influencementioning

confidence: 99%

Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA

Wojciechowski,

Marcinek,

Pleskacz

2023

Electronics

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“…To moderate an excessive requirement of high clock frequency, instead of poor counter method, the hybrid method is used [11][12][13][14][15][16][17][18]. The hybrid quantizer converts the MSB) [( 1) : ] rq Nmdata using counter method, while the remaining part of the LSB[(…”

Section: A System Clock Selection and Timingmentioning

confidence: 99%

International Journal of Electronics and Telecommunications

Kolodziejski

Kuta

2020

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“…Te high-resolution means that small frequency changes can be detected. Tere are many methods that have been developed to obtain a high-resolution frequency counter by using high-frequency reference clock [11], FFT [12], TDC [13,14], and others. However, the selection of this method needs to be selected by the application and capabilities of the device used.…”

Section: Introductionmentioning

confidence: 99%

Four-Channels High-Resolution Frequency Counter for QCM Sensor Array Using Generic FPGA XC6SLX9 Board

Triqadafi

Zafirah

Dharmawan

et al. 2023

Journal of Electrical and Computer Engineering

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A frequency counter is essential for resonance-based sensors like quartz crystal microbalance. An electronic nose or tongue using a QCM sensor array requires a multichannel frequency counter to detect the frequency shift of the sensors simultaneously. The frequency counter’s resolution, precision, and sampling speed are important factors. Board size, energy consumption, and rapid deployment are also considered in the design. This work shows the development of an independent multichannel frequency counter using a commercial Xilinx Spartan 6 series XC6SLX9 board module and a microcontroller board. Both modules are general-purpose modules; therefore, there is no need for a printed circuit board design, resulting in a quick implementation: the use of FPGA results in a compact size and low energy consumption. The developed counter is designed based on a reciprocal counter utilizing the internal logic block of the FPGA. The FPGA module has a built-in 50 MHz TCXO clock and is the reference clock. The high-resolution timing of the counter is realized by multiplying the 50 MHz clock by 6 to reach 300 MHz. The multiplication utilizes the PLL modules in the FPGA. The high precision and accuracy of the counter are achieved by calibrating the timing clock to a 10 MHz rubidium oscillator. The data communication to the microcontroller is done via the SPI by implementing the SPI protocol in the FPGA. The resource is optimized by utilizing PLL and DSP blocks for the counter. Only 5% registers and 5% LUTs of the FPGA resource are used to build a four-channel frequency counter. The result shows that the counter can measure the frequency of incoming signals with a resolution of 0.033 Hz at 10 MHz with a sampling time of 1 second. The system has been tested to monitor the frequency changes of a QCM sensor array.

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A High Resolution Vernier Digital-to-Time Converter Implemented with 65 nm FPGA

Cited by 8 publications

References 14 publications

Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA

Relative Jitter Measurement Methodology and Comparison of Clocking Resources Jitter in Artix 7 FPGA

International Journal of Electronics and Telecommunications

Four-Channels High-Resolution Frequency Counter for QCM Sensor Array Using Generic FPGA XC6SLX9 Board

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