A high-speed conditional carry select (CCS) adder circuit with a successively incremented carry number block (SICNB) structure for low-voltage VLSI implementation

Huang, Yen-Mou; Kuo, J.B.

doi:10.1109/82.877148

Cited by 9 publications

(4 citation statements)

References 8 publications

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“…3 shows the structure of improved Wallace tree. The structure is good in symmetry, regularity and easy implement for layout [5].…”

Section: The Design Of Structure and Algorithm Researchmentioning

confidence: 99%

Full-Custom Design and Implementation of High-Performance Multiplier

Wang

2013

AMR

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I proposed a method of using full-custom design 32 × 32 multiplier to enhance performance, reduce the power consumption and the area of layout. I use improved Wallace tree structure for partial product compression, truncated beyond the 64 part of the plot and the look-ahead logarithmic adder using Radix-4 Kogge-Stone tree algorithm raise the multiplier performance. In the design of Booth2 encoding circuit and compression circuit, I use a transmission gate logic design with higher speed and smaller area. I also use Euler path method and heuristic Euler path method to reduce the layout area. The design use SMIC 0.18μm 1P4M CMOS process, with a layout area of 0.1684mm2. In a large number of test patterns, simulation results show that the computation time of a 32 × 32 multiplication is less than 3.107ns.

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“…3 shows the structure of improved Wallace tree. The structure is good in symmetry, regularity and easy implement for layout [5].…”

Section: The Design Of Structure and Algorithm Researchmentioning

confidence: 99%

Full-Custom Design and Implementation of High-Performance Multiplier

Wang

2013

AMR

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“…A hybrid CLA/ CSA proposed by Wang, Pai, and Song (2002) reduces 1/3 of the critical path delay compared to conventional adders, but its area and power penalty is higher because of its CLA unit. Similarly, Poli (2004, 2011) and Huang and Kuo (2000) proposed different design approaches for CSA for minimising its delay but not on optimising its power and area.…”

Section: Introductionmentioning

confidence: 98%

Power and area-optimised Carry-Select Adder architecture for standard cell-based design

Shanmugam

Choi

2014

International Journal of Electronics

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A Carry-Select Adder (CSA) is one of the most suitable adders for high-speed applications, but the power and area penalties are greater, because it requires a double Ripple-Carry Adder (RCA) structure corresponding to carry inputs 0 and 1. Current low-power and low-area techniques are not suitable for a standard cell-based design which is one of the widely adopted design methodologies. Our work proposes two simple optimised architectures suitable for standard cell-based designs. A simple decision logic that replaces the RCA for Carry input 1 in a conventional CSA is proposed. One of the proposed architectures reduces power and area significantly with a small delay penalty compared to the existing techniques. Another proposed architecture improves the speed of operation and reduces the power and area considerably. The first one is more suitable for high-speed arithmetic in battery-operated applications where there is a trade-off between speed and power, while the other one is suitable for high-performance applications which also require area and power optimisation. The proposed architectures were implemented in TSMC 0.18um CMOS technology, and compared with conventional Square Root Carry-Select Adders and an existing standard cell-based design.

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“…A CPU's adder circuit is largely responsible for its speed performance. It has been observed that cer-2 tain adder circuits can perform faster [3] but with more Power consumption. To address the issues with power usage, a FinFET based carry select adder (CSA) is proposed which consumes less power than MOSFET [4].…”

Section: Introductionmentioning

confidence: 99%

“…The SUM generated by HA0 and Ex1_0 adder is given to 2-1M _1 which produces S[0] and then CARRY generated by HA0 and Ex1_0 is given to 2-1M_2 which produces C[0].In this PCSA the Carry propagation is done through The generated C[0] is propagated through 2-1M_3 which provides S[1] as output with respect to Cin (0 or 1). Similarly, S[2], S[3], and C[1], C[2], Cout are generated. (i) CMOS Excess-1 adder using 2-1M (ii) TGL Excess-1 adder using 2-1M…”

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confidence: 99%

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

Battini

PASHYA

Sivani

2023

Preprint

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Conventional carry select adder (CCSA) uses a multiplexer in the final stage to select either an excess-1 result or a normal result. To improve the delay and number of transistors a new topology is Proposed (PCSA) that uses only a single type of cell i.e., a 2 − 1 multiplexer. The 2 − 1 multiplexer is constructed in CMOS and TGL logic styles using 18nm FinFETs. The sub-blocks such as half adder and excess-1 circuit used in this PCSA is realized using only a 2:1 multiplexer. Due to the usage of a single type 2:1 multiplexer, the PCSA exhibits better circuit regularity. The new topology of PCSA is designed using FinFET-based TGL and CMOS styles. All the adders such 4- and 8-bit are designed, simulated, and analyzed using Cadence Virtuoso, ADEL, and ADEXL at 18nm FinFET technology. The result analysis reveals that the speed performance and the number of transistors of 8-bit PCSA are better by 44.02% and 4% respectively compared to existing adders.

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A high-speed conditional carry select (CCS) adder circuit with a successively incremented carry number block (SICNB) structure for low-voltage VLSI implementation

Cited by 9 publications

References 8 publications

Full-Custom Design and Implementation of High-Performance Multiplier

Full-Custom Design and Implementation of High-Performance Multiplier

Power and area-optimised Carry-Select Adder architecture for standard cell-based design

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

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