A High Speed Flash Analog to Digital Converter

Kumar, K. Sai; Krishna, K. Lokesh; Raghavendra, K. Sampath; Harish, K.S.

doi:10.1109/i-smac.2018.8653782

Cited by 8 publications

(2 citation statements)

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“…Under these discharging conditions, the resulting common mode current flows through the tail transistor. Due to this the gate to source voltage of the input differential paper consisting of MOS transistors M 1 and M 2 is reduced, and thus creates a dynamic biasing voltage for the input differential pair [17]- [18]. The voltage keeps reducing until the effective voltage at the source of both the M 1 and M 2 transistors reach the minimum value of difference between inverting input, non-inverting input and threshold voltages.…”

Section: Figure 2 Strongarm Comparator Circuitmentioning

confidence: 99%

“…The simulation results in 0.065micrometer technology report that the operating speed enhances by almost 50% at a bandwidth of 3gigahertz. K.S.Kumar et al described the design of a low offset voltage and high speed double-tail comparator for use in comparator array of a flash analog to digital converter architecture [8]. The comparator circuit is operated at VDD=1.8V and consumes power of 0.124mW.…”

Section: Introductionmentioning

confidence: 99%

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An Enhanced Strong ARM Comparator Circuit for Analog to Digital Converter Architectures

Adhithya

2024

IJRASET

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Technological innovations in the current century period have motivated professionals to make electronic gadgets smarter. These advancements are progressing at a brisk pace, facilitating faster changes and increase in computing power. Various technologies such as virtual reality, augmented reality, mobile internet, artificial intelligence, cloud computing, biometric devices, 3D printing machines, genomics, quantum computing, block-chain, industrial automation and robotics. In all these technologies, communications with nearby devices play a major role in its effective functioning. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power CMOS receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 180nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.8V, a clock frequency of 50MHz

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Section: Figure 2 Strongarm Comparator Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%