A high speed FPGA implementation of the 2D DCT for Ultra High Definition video coding

Efficient architecture of variable size HEVC 2D-DCT for FPGA platforms

“…Our proposed architecture enables variable block size (4×4, 8×8, 16×16 and 32×32), while the references [18,[20][21] only support one smaller block size (8×8 or 16×16). The references [18,[20][21] do not utilize on-chip DSP blocks. Due to the use of on-chip DSPs, our proposed work results in much shorter critical path and significant improvement in terms of frequency and throughput.…”

“…Yet, because there are no power consumption values available in references [18] and [21], we cannot include power consumption for a quantitative comparison in Table II. Alternatively, we offer a comprehensive analysis as below.…”

“…Therefore, the study of HEVC FPGA implementation is gaining more and more attention. In order to satisfy real-time and high-efficiency coding in these emerging video applications, a few design methodologies and circuit architectures have been developed [11,[18][19][20][21][22][23][24]. In [11], the authors presented an IDCT implementation with zero-column skipping technique to boost energy and area efficiency.…”

“…These approaches are efficient for smaller DCT computation (e.g., 8×8). The proposed architectures in [19][20][21] did not consider internal features and characteristics of FPGA platforms. In [22], a new algorithm and processing architecture for 2D-DCT were presented to achieve higher energy efficiency.…”

“…A series of hardware minimization techniques was applied, including operation reordering, multiplications to shift-adds conversion, etc. In [19][20][21], the proposed designs utilized distributed arithmetic hardware to perform multiplications in 2D-DCT. These approaches are efficient for smaller DCT computation (e.g., 8×8).…”