A high-speed, low-power 3D-SRAM architecture

Abstract

This paper presents a novel 3D-SRAM architecture that can be used to extend the scaling of SRAM. This architecture significantly reduces the bit-line capacitance, achieves 3.4 times reduction in active power consumption and 1.8 times reduction in access time. In this architecture, local bit-lines are vertical and connect through select transistors to the global bit-lines routed on the bottom level. A proof-of-concept 32Kb sub-array emulating the critical path of the 3D-SRAM has demonstrated about 5 times improvement in power-delay over conventional 2D-SRAM.

CiM3D: Comparator-in-Memory Designs Using Monolithic 3-D Technology for Accelerating Data-Intensive Applications

“…M3D process is a technology enabler for increasing memory densities and reducing access costs. Nho et al [25] and Kong et al [26] propose multi-layer 3D-SRAMs where the bitlines are folded into multiple layers with M3D vias. Reduction in delay and power is observed because of reduced bitline capacitance.…”

Three DIMENSIONAL-CHIPS

“…In our proposed 3D-SRAM architecture [9] shown in Fig. 3, the local bit-lines extend upward, through an inter-layer via that connects SRAM cells vertically.…”