A high-speed radix-4 multiplexer-based array multiplier

Abstract

This paper presents a new radix-4 multiplexer-based array multiplier, based on a multiplication scheme shown in a previous work, where 4-to-1 multiplexers are used for the computation of partial products. In the proposed design, the rows of the array are reduced to the half, compared to the initial multiplexer-based scheme, as two bits from both operands are processed at each step. The proposed scheme is compared to the Modified-Booth array multiplier and to the initial multiplexer-based array scheme. The compared designs are coded in VHDL and synthesized using the TSMC 0.13μm technology library. The synthesis results of critical time and area show 11-22% improvement in critical time delay compared to the Modified-Booth array, in the expense of an area overhead of 3.8-16%. Compared to the initial multiplexerbased scheme, there is a significant improvement in terms of area and critical time.