A High-Throughput Hardware Accelerator for Network Entropy Estimation Using Sketches

Tabular Interpolation Approach Based on Stable Random Projection for Estimating Empirical Entropy of High-Speed Network Traffic

“…However, no details were given of the traffic traces, measurement accuracy, or attainable throughput. Soto et al [44] presented a high-throughput hardware accelerator for estimating the entropy of network traffic, in which the estimation process focused mainly on the topk flows since the least frequent flows had no significant effect on the entropy of the data stream. The core of the accelerator consisted of a priority queue (PQ) array for the top-k flow selection and utilized the Count-Min sketch with Conservative Updates (CM-CU) [47] to evaluate the frequency statistics of the traffic flows.…”

“…As the cardinality estimation is outside the scope of this study, we refer the readers to the literature of Flajolet and Martin [57], [58] for the original algorithm. Furthermore, Kulkarni et al [59] and Soto et al [44] presented the estimation accelerator in FPGAs, and Ding et al [45] introduced the practical implementations in the P4 programming language.…”

“…The average resource consumption of the final implementation (kp = 20, mp = 1) using eleven pipeline stages is shown in Table 8. Figure Typically, the network traffic analysis adopts observation epochs of 30∼900 seconds [8], [41], [44]. Thus, based on the memory size ranging from 480 K to 640 K bytes, the proposed scheme can process traces of up to 98.8 million packets and handle approximately up to five million distinct items with less than 3% of mean absolute percentage error.…”

“…The designer can deploy the proposed schemes with a fair number of tables and hash functions based on the available memory space and processing throughput requirement. Thus, compared to the existing hardware solutions [8], [41], [44], [45] we can implement the proposed scheme in the programmable data plane with P4 on the Tofino Native Architecture (TNA) and FPGA easily. Moreover, instead of conducting read-modify-write operations (2~3 clock cycles) on the entire sketch memory [44], the read-only lookup procedure (1 clock cycle) of the proposed scheme provides a faster processing speed for the packet updates.…”

“…Thus, compared to the existing hardware solutions [8], [41], [44], [45] we can implement the proposed scheme in the programmable data plane with P4 on the Tofino Native Architecture (TNA) and FPGA easily. Moreover, instead of conducting read-modify-write operations (2~3 clock cycles) on the entire sketch memory [44], the read-only lookup procedure (1 clock cycle) of the proposed scheme provides a faster processing speed for the packet updates. Since the table lookup procedure can be performed in parallel, the latency is reduced.…”