A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace

Choi, Jung-Oh; Kim, Boyeal; Kim, Hyun; Lee, Hyuk-Jae

doi:10.1109/tvlsi.2018.2869663

Cited by 9 publications

(8 citation statements)

References 34 publications

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“…According to the analysis of memory requirement has been increasing whereas high throughput hardware devices can effectively compress the large amount of data in real application are needed. Hence, Choi et.al [28] proposed a high throughput based hardware architecture which can efficiently perform lossless IC operations. To mitigate hardware cost complexity issues due to the high throughput, authors utilized "Huffman" matrix is implemented, additionally, variable size streaming merge is performed at minimum cost rate by reducing the hardware size by mathematical Haffman coding operation.…”

Section: Related Workmentioning

confidence: 99%

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Design and Development of a Very Large Scale Integrated Circuit Architecture for a Digital Image Compression and Realization on Field Programmable Gate Array

2020

IJITEE

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The domain of image signal processing, image compression is the significant technique, which is mainly invented to reduce the redundancy of image data in order to able to transmit the image pixels with high quality resolution. The standard image compression techniques like losseless and lossy compression technique generates high compression ratio image with efficient storage and transmission requirement respectively. There are many image compression technique are available for example JPEG, DWT and DCT based compression algorithms which provides effective results in terms of high compression ratio with clear quality image transformation. But they have more computational complexities in terms of processing, encoding, energy consumption and hardware design. Thus, bringing out these challenges, the proposed paper considers the most prominent research papers and discuses FPGA architecture design and future scope in the state of art of image compression technique. The primary aim to investigate the research challenges toward VLSI designing and image compression. The core section of the proposed study includes three folds viz standard architecture designs, related work and open research challenges in the domain of image compression.

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Section: Related Workmentioning

confidence: 99%

“…Only suitable to hardware implementation Choi et.al [28] To design a high-throughput hardware device for IC…”

Section: D-dwt and Har Wavelet Psnr Ssim And Cw-ssimmentioning

confidence: 99%

Design and Development of a Very Large Scale Integrated Circuit Architecture for a Digital Image Compression and Realization on Field Programmable Gate Array

2020

IJITEE

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“…For Huffman encoding, reference [9] proposes a parallel coding. Literature [10] introduces binary tree Huffman coding; Literature [11] proposes canonical Huffman encoding and [12] [13] uses static random access memory and bitmap to implement Huffman tree encoding. But these Huffman encodes will still have blockage.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Fast Huffman Encoding Based on FPGA

Shan

Chen

Qiu

et al. 2022

J. Phys.: Conf. Ser.

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In order to improve the efficiency of JPEG encoding architecture, some imagine compression systems use pipeline technology. Different modules will spend different cycles in the image compression, so the pipeline is prone to blockage. This paper proposes uses doublebyte splicing output Huffman code architecture and double Huffman encoding units on FPGA, so that Huffman encoding process spent less clock cycles in JPEG encoding, and pipelined JPEG encoding algorithm can be encoded in real time without blocking. According to the FPGA verification, although the number of logic units used will increase, Huffman encoding takes less clock cycles.

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“…A hardware acceleration approach for integrated circuits compression is introduced in Halawani et al [15]. Choi et al [16] have considered hardware throughput approach for on-chip compression. A compression scheme for image sensors is presented in Kaur et al [17] by using interpolation operation over the on-chip hardware design.…”

Section: Introductionmentioning

confidence: 99%

Novel hybrid framework for image compression for supportive hardware design of boosting compression

Premachand¹,

Eranna²

2021

IJECE

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Performing the image compression over the resource constrained hardware is quite a challenging task. Although, there has been various approaches being carried out towards image compression considering the hardware aspect of it, but still there are problems associated with the memory acceleration associated with the entire operation that downgrade the performance of the hardware device. Therefore, the proposed approach presents a cost effective image compression mechanism which offers lossless compression using a unique combination of the non-linear filtering, segmentation, contour detection, followed by the optimization. The compression mechanism adapts analytical approach for significant image compression. The execution of the compression mechanism yields faster response time, reduced mean square error, improved signal quality and significant compression ratio performance.

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A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace

Cited by 9 publications

References 34 publications

Design and Development of a Very Large Scale Integrated Circuit Architecture for a Digital Image Compression and Realization on Field Programmable Gate Array

Design and Development of a Very Large Scale Integrated Circuit Architecture for a Digital Image Compression and Realization on Field Programmable Gate Array

Implementation of Fast Huffman Encoding Based on FPGA

Novel hybrid framework for image compression for supportive hardware design of boosting compression

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