A High Throughput QC-LDPC Decoder Architecture for Near-Earth Satellite Communication

Nampoothiri, K. M. Sankar; Menon, Kalyani N; Muhsin, Sayed; Manoj, Senna; Sooraj, P; Dhanaraj, K. J.; Deepthi, P. P.

doi:10.1109/iccss51193.2021.9464195

Cited by 4 publications

(4 citation statements)

References 11 publications

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“…Promising results show that 13.3Gb/s is achieved with 5 decoders on one FPGA device, with less than 75% resources. Decoders proposed in [12], [21] achieve high throughput at the cost of high resource consumption. The throughput of our proposed decoder, when utilizing a combination of five decoders, surpasses that of the decoder in [12] by 1.3 times, while also achieving a 50% reduction in resource utilization.…”

Section: Fpga Implementation and Analysismentioning

confidence: 99%

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Universal High-Throughput and Low-Complexity LDPC Decoder for Laser Communications

Kang,

An,

Zhu

2024

IEEE Access

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To address the challenges posed by propagation channel impairments and to meet the high data rate requirements of laser communications, this study introduces a pioneering low-density parity-check (LDPC) decoder characterized by its high throughput and low complexity. The unique design of this decoder, based on an inter-frame pipeline and intra-frame parallel (IFPP-IFP) scheme, is specifically tailored to maximize the efficiency of processing units, leading to a substantial increase in decoding throughput. The implementation of IFPP is realized through a novel full-overlap message passing (FOMP) scheme and a dynamic address access (DAA) algorithm, distinguishing it from current solutions. Additionally, the decoder employs a message packing strategy and low-complexity data alignment units to effectively achieve IFP. Compared to existing solutions, our hardware implementation on the Xilinx XCKU060 FPGA demonstrates significant progress. The decoder achieves a decoding throughput of 2.67 Gb/s at 10 iterations and 350MHz. Remarkably, when five decoders are used on a single FPGA device, the throughput soars to 13.3 Gb/s, outperforming state-of-the-art designs by 1.3 times and concurrently reducing resource consumption by half. This combination of resource efficiency and enhanced throughput highlights the innovative and superior nature of our proposed approach.

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Section: Fpga Implementation and Analysismentioning

confidence: 99%

“…In [20], compact memory strategies for partially parallel QC-LDPC decoder architecture are proposed and achieve a throughput up to 2 Gb/s. The decoder in [21] is implemented on the Xilinx XCVU9P FPGA and achieves a throughput of 2.65 Gb/s.…”

Section: Introductionmentioning

confidence: 99%

Universal High-Throughput and Low-Complexity LDPC Decoder for Laser Communications

Kang,

An,

Zhu

2024

IEEE Access

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“…Quasi-Cyclic Low-density Parity Check Codes, which are structured LDPC codes, are used in this work. It has been suggested that Quasi-Cyclic can be used to streamline LDPC and still produce equivalent outcomes [13].…”

Section: Figure2 Evaluation Of Error Correcting Codesmentioning

confidence: 99%

“…There are multiple decoding strategies for QC-LDPC codes in order to preserve the trade-offs between hardware complexity, decoding efficiency, and error-correction performance. The efficiency of iterative message passing techniques for error correction is excellent despite their high decoding complexity[15Despite having a relatively high decoding complexity, the best decoding performance is achieved by a Sum-Product Algorithm (SPA) based on soft judgements [5,13]. A number of changes have been suggested to make the SPA's check node function simpler.…”

Section: Figure2 Evaluation Of Error Correcting Codesmentioning

confidence: 99%

A Quasi-Cyclic LDPC Based Low Complexity and Area-Efficient Communication System for IEEE 802.11n

Yashika Gaidhani, Tejaswini Panse

2024

jes

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Low-density parity-check (LDPC) code, which has an excellent error-correcting performance that is close to the Shannon limit, is the most often used error correction code (ECC) for reliable and effective communication. Despite higher performance and lower decoding complexity, the main disadvantage of LDPC codes is their high encoding complexity. A significant problem is the VLSI implementation of the LDPC encoder and decoder. In this paper, structured LDPC codes—also known as quasi-cyclic low-density parity check codes—have been used since it is good bit error ratio (BER) performance and adaptable hardware execution characteristics. The Complete (Encoder-Channel-Decoder) communication system with a 1/2 code rate, 648 bits codeward length, and sub-block size of z = 27 has been constructed for the IEEE 802.11n wireless standard.

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High-Throughput LDPC Encoder/Decoder for Real-Time Coherent Optical Communications

Chen,

Zhang

et al. 2024

2024 Asia Communications and Photonics Conference (ACP) and International Conference on Information Photonics and Optical Commu

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A High Throughput QC-LDPC Decoder Architecture for Near-Earth Satellite Communication

Cited by 4 publications

References 11 publications

Universal High-Throughput and Low-Complexity LDPC Decoder for Laser Communications

Universal High-Throughput and Low-Complexity LDPC Decoder for Laser Communications

A Quasi-Cyclic LDPC Based Low Complexity and Area-Efficient Communication System for IEEE 802.11n

High-Throughput LDPC Encoder/Decoder for Real-Time Coherent Optical Communications

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