A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter

Wang, Hua; Peng, Chun-Hsien; Chang, Yaopei; Huang, Richard; Chang, Chih-Wei; Shih, Xin-Yu; Hsu, Chia-Jui; Liang, Paul; Niknejad, Ali M.; Chien, George; Tsai, Chao Long; Hwang, Hoyong

doi:10.1109/tcsi.2014.2309811

Cited by 45 publications

(9 citation statements)

References 6 publications

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“…Various trade-offs between resolution and clock rates have been used in digital to RF conversion (DRFC) approaches, embedding the DAC into the baseband to RF mixer. Examples are the 6-bit switched-capacitor (SC) I/Q sharing DRFC structure in [2] or the 13-bit RF power DAC in [3], which present significant conceptual differences, since [2] optimizes power efficiency using a low-resolution scheme, and [3] targets improved noise performance thanks to additional resolution and digital pre-distortion. In [4], a 10-bit currentsteering DAC is demonstrated and digital Delta-Sigma Modulators (ΔΣM) with mismatch shaping (MS) are used to reduce OOB emissions at a programmable duplex distance.…”

Section: A Speed Vs Resolution Trade-off In Digital Transmittersmentioning

confidence: 99%

Digital RF Transmitter With Single-Bit $\Delta\Sigma$ M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI

Marin¹,

Frappé²,

Stefanelli³

et al. 2019

IEEE Trans. Microwave Theory Techn.

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This paper presents a single-bit RF transmitter based on single-bit switched-capacitor RF digital-to-analog converters (DAC) embedded in an FIR filter (FIR-DAC). The transmitter system comprises a single-bit quadrature Delta-Sigma Modulator (ΔΣM), a digital mixer, and a 109-tap RF FIR-DAC stage with a single external inductor, combining D-A conversion with discrete and continuous time filtering. The onchip part of the FIR-DAC is built exclusively with CMOS inverters and Metal-Oxide-Metal (MOM) capacitors, which are implemented in the interconnect layers to propose a compact fully-digital solution, suitable for advanced CMOS nodes.A method for canceling redundant switching in the FIR-DAC is proposed to reduce its complexity and power consumption. Combining discrete and continuous-time filtering, the out-ofband quantization noise of the 1-bit RF signal is strongly attenuated below the level required by emission masks. The RF FIR-DAC prototype is implemented in 28nm FD-SOI CMOS technology with 10 metal layers and occupies a total active area of only 0.047 mm 2 . The overall power consumption is 38 mW at 4.6 dBm peak output power, 900 MHz carrier frequency and 1 V supply. FD-SOI body-bias Vt tuning is used to effectively correct mixing clock duty-cycle errors in order to perform precise highfrequency I/Q interleaving, which enables high image and local oscillator (LO) rejections. The resulting power consumption, surface and performance of the measured prototype make the proposed circuits and concepts particularly appropriate for use in emerging Internet of Things (IoT) applications.

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Section: A Speed Vs Resolution Trade-off In Digital Transmittersmentioning

confidence: 99%

Digital RF Transmitter With Single-Bit $\Delta\Sigma$ M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI

Marin¹,

Frappé²,

Stefanelli³

et al. 2019

IEEE Trans. Microwave Theory Techn.

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“…The most stringent noise specifications are found for the GPS band around 1575 MHz, due to the low typical power level of the GPS signal (~ -125 dBm). This issue has been highlighted in [2], where a noise floor of -130 dBm/Hz is measured in the GPS band when transmitting an 802.11g 54 Mbps signal on Channel 1 with a power of 16.35 dBm. In addition, the same noise requirements apply to the GLONASS band around 1602 MHz (27 MHz away from GPS).…”

Section: A Out-of-band Noise Vs Multi-standard Coexistencementioning

confidence: 99%

Digital Complex Delta–Sigma Modulators With Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters

Marin

Frappé

2018

IEEE Trans. Circuits Syst. I

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This paper presents a Complex Delta-Sigma Modulator (CDSM) designed for the integration in a digital transmitter chain targeting multi-standard coexistence with nearby receivers. The use of a Delta-Sigma Modulator (DSM) has the advantage of increased performances in terms of signal-tonoise-ratio (SNR) in the band of interest. However, the resulting out-of-band noise becomes an issue for multi-standard coexistence, thus increasing the complexity of the succeeding filtering stage. These constraints could be relaxed in the DSM stage, by placing a complex zero near the frequency band, where a low noise level is needed. This is achieved by cross-coupling the In-phase (I) and Quadrature (Q) channels, thus obtaining a CDSM. A review of known design methods for CDSM revealed limitations regarding the poles/zeros optimization, and the configurability of the complex zeros placement. The proposed architecture introduces two additional cross-couplings from the I and Q quantizers' outputs in order to decorrelate the zeros placement and the poles optimization problem. Hence, the improved CDSM can be implemented using existing optimization tools, which reduces considerably the number of iterations and the computational effort. In addition, the resulting modulator can target different coexistence scenarios without the need of redesign, unlike other known methods. Simulation results show a noise level reduction of approximately 20-30 dB near specific frequency bands by the proposed CDSM scheme with respect to standard DSM. Finally, we show an efficient fine/coarse configurability mechanism, which is obtained when introducing additional delays in the cross-coupling paths. Index Terms-Delta Sigma Modulator (DSM), Complex Delta Sigma Modulator (CDSM), finite impulse response (FIR), multistandard coexistence, digital transmitter; I. INTRODUCTION ECENT progress in advanced CMOS integrated digital transmitter (TX) architectures [1] [2] has been focusing on reducing the power consumption and circuit area to follow the trend of increased data rates and signal bandwidths (BW) in communication standards, e.g. IEEE 802.11 standard.

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“…This can be achieved by performing a final AND with the 2LO signal before the conversion cell [42]. Such an arrangement has the additional advantage to hide the skews between different data bits [45], since the transitions of all c P and c N signals take place during the low phase of 2LO. The differential encoding ensures nearly constant current flow from the power supply, thus eliminating signaldependent IR drop.…”

Section: Rf Front-endmentioning

confidence: 99%

All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise

Roverato

Kosunen

Cornelissens³

et al. 2017

IEEE J. Solid-State Circuits

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We present the first all-digital LTE transmitter using programmable digital attenuation of RX-band noise. The system is architectured to fully exploit the speed and low cost of DSP logic in deep-submicron CMOS processes, without increasing at all the design effort of the RF circuitry. To achieve SAWless operation, the transmitter uses digital bandpass delta-sigma modulation and mismatch-shaping to attenuate the DAC noise at a programmable duplex distance. These functions can be implemented entirely within DSP, thus taking advantage of the standard digital design methodology. Furthermore, the fully digital RX-band noise shaping significantly relaxes the performance requirements on the RF front-end. Therefore, 10 bits of resolution for the D/A conversion are sufficient to achieve-160 dBc/Hz out-of-band noise, without need for digital predistortion, calibration or bulky analog filters. The transmitter was fabricated in 28nm CMOS, and occupies only 0.82 mm 2. Besides low outof-band noise, our system also demonstrates state-of-art linearity performance, with measured CIM3/CIM5 below-67 dBc, and ACLR of-61 dBc with LTE20 carrier. The circuit consumes 150 mW from 0.9/1.5V supplies at +3 dBm output power.

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A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter

Cited by 45 publications

References 6 publications

Digital RF Transmitter With Single-Bit $\Delta\Sigma$ M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI

Digital RF Transmitter With Single-Bit $\Delta\Sigma$ M-Driven Switched-Capacitor RF DAC and Embedded Band Filter in 28-nm FD-SOI

Digital Complex Delta–Sigma Modulators With Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters

All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise

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