A highly parallel SAD architecture for motion estimation in HEVC encoder

Medhat, Ahmed; Shalaby, Ahmed; Sayed, Mohammed S.; Elsabrouty, Maha; Mehdipour, Farhad

doi:10.1109/apccas.2014.7032774

Cited by 28 publications

(13 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…For absolute difference calculation, one method is to detect the smaller operand in the absolute difference computation |CB−RB| and to subtract it from the larger operand [4], [5].The other method comprises of complimenting the smaller of the two numbers and then performing addition of two numbers followed by plus one to compute the absolute difference [6]. To compute the absolute difference for SAD, in [7] a novel architecture is optimized for realizing efficient absolute difference circuits in Virtex-5 FPGA devices which uses the 6-input look-up tables available within the chosen devices family to maximize speed performance and to minimize the amount of occupied resources.…”

Section: Related Workmentioning

confidence: 99%

“…Hardware architecture for computing the absolute difference between corresponding pixels in current and reference video block is proposed. The method used for AD calculation is as used in [6] where adder and comparator form the basic component as shown in Figure 1.The 8-bit comparator compares two numbers and returns the 1's complement of the smaller number and the larger number as it is. Proposed Architecture: In this architecture:…”

Section: Proposed Architecturementioning

confidence: 99%

See 1 more Smart Citation

Efficient Absolute Difference Circuit for SAD Computation On FPGA

Koshta

Khare

Gupta

2019

VLSICS

View full text Add to dashboard Cite

Video Compression is very essential to meet the technological demands such as low power, less memory and fast transfer rate for different range of devices and for various multimedia applications. Video compression is primarily achieved by Motion Estimation (ME) process in any video encoder which contributes to significant compression gain.Sum of Absolute Difference (SAD) is used as distortion metric in ME process.In this paper, efficient Absolute Difference(AD)circuit is proposed which uses Brent Kung Adder(BKA) and a comparator based on modified 1's complement principle and conditional sum adder scheme. Results shows that proposed architecture reduces delay by 15% and number of slice LUTs by 42 % as compared to conventional architecture. Simulation and synthesis are done on Xilinx ISE 14.2 using Virtex 7 FPGA. KEYWORDSHEVC, motion estimation, sum of absolute difference, parallel prefix adders, Brent Kung Adder.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Proposed Architecturementioning

confidence: 99%

Efficient Absolute Difference Circuit for SAD Computation On FPGA

Koshta

Khare

Gupta

2019

VLSICS

View full text Add to dashboard Cite

show abstract

“…This architecture is generally utilised for low resolution video data along with less complex applications. In [9] a highly parallel SAD architecture for motion estimation in HEVC encoder is presented where there are sixty four processing units which are operating in parallel for computation of SAD values in ME unit. Here the architecture utilises separate two memory banks one for Reference CTB and other for Instantaneous CTB.…”

Section: Related Workmentioning

confidence: 99%

High Speed Parallel SAD Architecture Implementation on FPGA for HEVC encoder

Koshta*,

Khare

2019

IJEAT

View full text Add to dashboard Cite

Video compression is a very complex and time consuming task which generally pursuit high performance. Motion Estimation (ME) process in any video encoder is responsible to primarily achieve the colossal performance which contributes to significant compression gain. Summation of Absolute Difference (SAD) is widely applied as distortion metric for ME process. With the increase in block size to 64×64 for real time applications along with the introduction of asymmetric mode motion partitioning(AMP) in High Efficiency Video Encoding (HEVC)causes variable block size motion estimation very convoluted. This results in increase in computational time and demands for significant requirement of hardware resources. In this paper parallel SAD hardware circuit for ME process in HEVC is propound where parallelism is used at various levels. The propound circuit has been implemented using Xilinx Virtex-5 FPGA for XC5VLX20T family. Synthesis results shows that the propound circuit provides significant reduction in delay and increase in frequency in comparison with results of other parallel architectures.

show abstract

“…Its hardware implementation can be helpful for the video encoder. In the literature, many works are proposed to support the SAD architecture for several application domains, such as computer vision, like motion detection for image processing [6], on the system video surveillance based motion detection and recognition in [7], that it implements on an embedded board based on XC2V1000 FPGA and motion estimation for video compression standards [8,9,10,11,12,13,14]. All the proposed architectures aim to reach real-time processing for higher resolutions sequences with the highest possible operating frequency and to compute the maximum inter-prediction blocs whatever their sizes.…”

Section: Introductionmentioning

confidence: 99%

“…The synthesis shows an operating frequency of 110 MHz with 55346 LUTs, 19744 registers, and 148kB of BRAM. More recently, Medhat et al [14] proposed a parallel hardware SAD accelerator for the motion estimation, synthetized on a Xilinx Virtix-7 XC7VX550T FPGA. An operating frequency of 458 MHz has been reported with 39901 LUTs and 24957 registers.…”

Section: Introductionmentioning

confidence: 99%

Area & Power Efficient VLSI Architecture of Mode Decision in Integer Motion Estimation for HEVC Video Coding Standard

Abdessamad¹,

Bahri²,

Mansouri³

et al. 2019

IJECE

View full text Add to dashboard Cite

<span lang="EN-US">In this paper, we propose a new parallel hardware architecture for the mode decision algorithm, that it is based on the Sum Absolute of the Difference (SAD) for compute the motion estimation, which is the most critical algorithm in the recent video encoding standard HEVC. In fact, this standard introduced new large variable block sizes for the motion estimation algorithm and therefore the SAD requires a more reduced execution time in order to achieve the real time processing even for the ultra-high resolution sequences. The proposed accelerator executes the SAD algorithm in a parallel way for all sub-block prediction units (PUs) and coding unit (CU) whatever their sizes, which turns in a huge improvements in the performances, given that all the block sizes, PUs in each CU, are supported and processed in the same time. The Xilinx Artix-7 (Zynq-7000) FPGA is used for the prototyping and the synthesis of the proposed accelerator. The mode decision for motion estimation scheme is implemented with 32K LUTs, 50K registers and 108Kb BRAMs. The implementation results show that our hardware architecture can achieve 30 frames per second of the 4K (3840 × 2160) resolutions in real time processing at 115.15MHz.</span>

show abstract

A highly parallel SAD architecture for motion estimation in HEVC encoder

Cited by 28 publications

References 12 publications

Efficient Absolute Difference Circuit for SAD Computation On FPGA

Efficient Absolute Difference Circuit for SAD Computation On FPGA

High Speed Parallel SAD Architecture Implementation on FPGA for HEVC encoder

Area & Power Efficient VLSI Architecture of Mode Decision in Integer Motion Estimation for HEVC Video Coding Standard

Contact Info

Product

Resources

About