A highly reliable NBTI Resilient 6T SRAM cell

Singh, Jawar; Narayanan, Vijaykrishnan

doi:10.1016/j.microrel.2012.11.003

Cited by 5 publications

(1 citation statement)

References 21 publications

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“…Due to the susceptibility of the CMOS inverter to latch‐up and the higher effect of NBTI on PMOS transistors, an N‐type MOS (NMOS) only buffer may be used for the output buffer [3, 4]. At the same time, Schmitt trigger (ST) can be used when an input signal changes its value very slowly, and values bounce between two voltage levels, we need a circuit with hysteresis to shape the input waveform into one with fast transition time.…”

Section: Introductionmentioning

confidence: 99%

NMOS only Schmitt trigger circuit for NBTI resilient CMOS circuits

et al. 2018

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A novel N-type MOS (NMOS) only Schmitt trigger with voltage booster (NST-VB) circuit is presented. The proposed NST-VB circuit uses NMOS transistors in both pull-up and pull-down networks to reduce the effect of negative bias temperature instability (NBTI) on the circuit. The proposed circuit is less affected by both inter-die and intra-die process variations in consequence of NMOS only structure. Owing to NBTI, the increase in delay for the proposed NST-VB circuit is only 0.47% as compared with 7.2% for conventional Schmitt trigger after the stress time of three years. For the viability of the proposed circuit figure of merit (FOM) is used as a performance metric and it is found that the proposed circuit has 15.35× and 3.53× improved FOM as compared with the conventional Schmitt trigger and NMOS inverter, respectively.

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Section: Introductionmentioning

confidence: 99%