A holistic approach to network-on-chip synthesis

Leary, Glenn; Chatha, Karam S.

doi:10.1145/1878961.1879001

Cited by 8 publications

(7 citation statements)

References 6 publications

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“…A genetic algorithm with similar capabilities is presented by Leary et al [7]. Leary and Chatha [8] presented a holistic LP approach that is able to handle port count constraints, specifications consisting of multiple use cases, and soft latency constraints. Khan and Tino [9] presented an iterative Tabu-search synthesis algorithm.…”

Section: Related Workmentioning

confidence: 99%

“…The mutual information is a measure that quantifies the statistical information shared between two distributions [28]. Equation (8) provides an expression for the normalized mutual information between two partitionings C a and C b . In the expression n is the total number of unique PE ports in C, n a h is the number of ports in cluster κ h according to C a , n b l is the respective number of ports in cluster κ l in C b , and n h,l is the number of shared ports between clusters κ h and κ l : …”

Section: System Partitioningmentioning

confidence: 99%

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Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies

Todorov

Mueller-Gritschneder

Reinig

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Networks-on-Chip (NoCs) enable cost-efficient and effective communication between the processing elements inside modern systems-on-chip (SoCs). NoCs with regular topologies such as meshes, tori, rings, and trees are well suited for general-purpose many core SoCs. These topologies might prove suboptimal for SoCs with predefined application characteristics and traffic patterns. Such SoCs benefit from application-specific NoC topologies, designed and optimized according to the application characteristics. This paper proposes a synthesis approach for creating hybrid, application-specific NoCs from an input floorplan and a set of use cases, describing the applications running on the SoC. The method considers latency, port count, and link length constraints. It produces hybrid topologies that utilize both NoC routers and shared buses. Furthermore, the proposed approach can insert intermediate relay routers that act as bridges or repeaters and help to reduce the cost further. Finally, the approach creates a deadlock-free routing of the communication flows by either finding deadlock-free paths or by inserting virtual channels. The benefits of the proposed method are demonstrated by comparing it to state-of-the-art approaches on a generic and an industrial SoC examples.

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Section: Related Workmentioning

confidence: 99%

Section: System Partitioningmentioning

confidence: 99%

Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies

Todorov

Mueller-Gritschneder

Reinig

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…then synthesize the NoC architecture for the sub-system. As mentioned earlier we utilize an existing approach to synthesize the NoC [2]. The NoC synthesis technique supports guaranteed throughput traffic which is ideal for streaming applications.…”

Section: System-level Memory Synthesismentioning

confidence: 99%

“…As the objective is to minimize the power consumption subject to both performance and area constraints the number (and sizes) of memory elements, and router nodes that can be utilized are limited. In our approach we utilize an existing NoC synthesis technique [2]. This paper presents a novel automated memory synthesis approach that is able to effectively perform the various trade-offs, and generate a highly optimized memory and NoC architecture for the sub-system.…”

Section: Introductionmentioning

confidence: 99%

System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC

Leary

Che

Chatha

2012

Proceedings of the 49th Annual Design Automation Conference

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Many embedded processor chips aimed at high performance and low power application domains are implemented as multiprocessor System-on-Chip (MPSoC) devices. The multimedia and communication sub-systems of an MPSoC perform some of the most computation intensive and performance critical tasks, and are key determinants of the systemlevel performance and power consumption. This paper presents an automated technique for synthesizing the system-level memory architecture (both code and data) for the streaming sub-systems of an embedded processor. The experimental results evaluate effectiveness of the proposed technique by synthesizing the system-level memory architecture for benchmark stream processing applications and comparisons against an existing approach.

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“…Interconnection and router synthesis/generation [9][10][11] are most studied for on-chip network designs due to their customized design requirements.…”

Section: Introductionmentioning

confidence: 99%

Analysis and synthesis techniques of router circuits

Lee

Huang

2015

2015 4th International Conference on Computer Science and Network Technology (ICCSNT)

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Along with continuing advancement of network and chip technology, vast amount of new router designs will be designed and utilized in differentiated Internet-connected systems, on-chip interconnection in SoC, and evolving softwaredefined networks. In this research, from an analysis of current and future router designs, we observe that router designs share a common composition structure. We thus devised synthesis techniques based on the common composition structure. It allows designers specifying high-level and detailed router design decisions. Together with extensible parts of router designs organized in the common structure, it can produce desirable synthesizable Verilog router designs. We implemented the synthesis design that is based on a number of synthesis techniques and HDL configuration generation method. Experimental results show that our approach can effectively produce desirable synthesizable Verilog router designs.

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A holistic approach to network-on-chip synthesis

Cited by 8 publications

References 6 publications

Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies

Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies

System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC

Analysis and synthesis techniques of router circuits

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