A Hybrid Approach for Efficient and Secure Point Multiplication on Binary Edwards Curves

Abstract

The focus of this article is to present a novel crypto-accelerator architecture for a resource-constrained embedded system that utilizes elliptic curve cryptography (ECC). The architecture is built around Binary Edwards curves (BEC) to provide resistance against simple power analysis (SPA) attacks. Furthermore, the proposed architecture incorporates several optimizations to achieve efficient hardware resource utilization for the point multiplication process over GF(2m). This includes the use of a Montgomery radix-2 multiplier and the projective coordinate hybrid algorithm (combination of Montgomery ladder and double and add algorithm) for scalar multiplication. A two-stage pipelined architecture is employed to enhance throughput. The design is modeled in Verilog HDL and verified using Vivado and ISE design suites from Xilinx. The obtained results demonstrate that the proposed BEC accelerator offers significant performance improvements compared to existing solutions. The obtained throughput over area ratio for GF(2233) on Virtex-4, Virtex-5, Virtex-6, and Virtex-7 Xilinx FPGAs are 9.43, 14.39, 26.14, and 28.79, respectively. The computation time required for a single point multiplication operation on the Virtex-7 device is 19.61 µs. These findings indicate that the proposed architecture has the potential to address the challenges posed by resource-constrained embedded systems that require high throughput and efficient use of available resources.

An Optimized Hardware Implementation of a Non-Adjacent Form Algorithm Using Radix-4 Multiplier for Binary Edwards Curves

“…Its effective design and potential for resource-sensitive applications are highlighted by the optimization's excellent 1.78 times greater throughput/area ratio. In a similar vein, our architectural solution uses 6.5 percent more hardware resources than [21]. Nevertheless, in terms of processing time in microseconds, it greatly outperforms the work in [21].…”

“…Although it is a little more resource-intensive, the large improvement in processing speed results in significant throughput benefits. Our design also outperforms [21] by utilizing 1.28 times fewer hardware resources with 1.38 times faster latency. As a result, 1.78 times greater throughput/area ratio is achieved.…”

“…Finally, the authors in [21] propose a hybrid algorithm for the optimization of BEC computations. The hybrid technique combines Montgomery and double-and-add techniques.…”

“…Our architecture uses 79.8% less hardware, operating 1.21 times faster, and achieves 6.04 times higher throughput/area efficiency, setting new benchmarks for computational power. Our architecture, which employs cutting-edge control flow techniques, performs 1.19 times quicker, achieves a stunning 1.57 times higher throughput/area efficiency, and uses 24.2 percent fewer hardware resources than [21]. Finally, our architecture effectively manages resources and control flow compared to [25].…”

“…Additionally, while our architecture uses slightly more hardware resources than [19], its processing time is significantly faster. Furthermore, our architecture effectively controls resources compared to [21], using only 1.07 times more hardware resources while operating 1.42 times quicker. Increasing the throughput/area ratio noticeably by 1.32-fold demonstrates its flexibility and effectiveness.…”