A Hybrid Approach to Fault Detection and Correction in SoCs

Bernardi, P.; Bolzani, L.; Reorda, Matteo Sonza

doi:10.1109/iolts.2007.8

Cited by 6 publications

(13 citation statements)

References 10 publications

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“…In the last years, a new family of cores, called Infrastructure Intellectual Property cores (I-IPs), has been introduced in order to improve (among the others) testing, silicon debugging, and diagnosis facilities in SoCs [15]. For example in [12] and [13] the authors report the use of I-IPs for testing and fault detection in microprocessor based systems. As it has been experimentally demonstrated, the inclusion of I-IPs in a microprocessor-based SoC does not generate system performance degradation, nor requires an excessive hardware overhead, while improving testing and diagnostic capabilities of the SoC.…”

Section: Introductionmentioning

confidence: 99%

A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs

Perez¹,

Velasco²,

Ravotto

et al. 2008

2008 14th IEEE International on-Line Testing Symposium

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Software-Based Self-Test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at-speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing, a particularly complex module to test is the cache controller, due to its limited accessibility and observability. In this paper we propose a hybrid methodology that exploits an Infrastructure Intellectual Property (I-IP) to complement an SBST algorithm for testing the data and instruction cache controllers of embedded processors in SoCs. In particular, the I-IP may be programmed to monitor the system buses and generate the appropriate feedback about the correct result of the executed programs (in terms of obtained hit or miss operations). The effectiveness of the proposed methodology is evaluated resorting to a sample SoC design.

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Section: Introductionmentioning

confidence: 99%

A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs

Perez¹,

Velasco²,

Ravotto

et al. 2008

2008 14th IEEE International on-Line Testing Symposium

Self Cite

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“…Algorithm Based Fault Tolerance (ABFT) [4], Assertions [5] and Code Flow Checking [6] belong to the second group. In [13] we proposed a hybrid fault detection and fault tolerance approach inspired by the software-based technique presented in [7]. The solution proposed in [13] combines some software modifications with the introduction of an I-IP to provide fault detection and correction capabilities.…”

Section: Introductionmentioning

confidence: 99%

“…In [13] we proposed a hybrid fault detection and fault tolerance approach inspired by the software-based technique presented in [7]. The solution proposed in [13] combines some software modifications with the introduction of an I-IP to provide fault detection and correction capabilities. The method mainly addresses faults affecting the data, but it can be easily complemented by other techniques addressing faults affecting the control flow, such as that proposed in [8].…”

Section: Introductionmentioning

confidence: 99%

“…The major advantage of that solution lies in its ability to supply fault tolerance towards transient faults with a relatively limited decrease of the performance with respected to the solution providing fault detection capabilities, only. In this paper we elaborate on the technique proposed in [13], and describe a set of optimizations, allowing to further decrease the impact of our technique on both the code size and the application performance. The effectiveness of the proposed approach has been evaluated on a sample SoC running a set of benchmark applications.…”

Section: Introductionmentioning

confidence: 99%

“…In Section 3 we outline the hybrid solution to detect and correct faults proposed in [13]. In Section 4 we describe the optimizations proposed, aiming at further decreasing the method's impact on code side and application performance.…”

Section: Introductionmentioning

confidence: 99%

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An optimized hybrid approach to provide fault detection and correction in SoCs

Bolzani

Bernardi

Reorda

2007

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

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An increasing number of safety-critical applications are based on Systems-on-Chip (SoCs), thus pushing a new wave of research aiming at the development of suitable techniques for ensuring their reliability. Several fault tolerance techniques have been proposed to ensure their fault detection capabilities, based either on software-based or hardware-based techniques. In this paper, we propose an optimized version of a recently proposed hybrid approach, which is able to provide fault detection and correction capabilities with respect to transient faults for processor-based SoCs. The proposed solution exploits some modifications of the source code at high level and an Infrastructure IP (I-IP). The main advantage of the proposed method lies in the fact that it does not require any modification of the microprocessor core. Experimental results show that the proposed method can guarantee fault coverage mainly at the same cost of the original method providing fault detection, only.

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