A hybrid ARM‐FPGA cluster for cryptographic algorithm acceleration

Abstract

Summary Clusters based on hybrid architectures combining ARM CPUs and FPGA fabric, such as the Xilinx Zynq SoC, not only are energy‐efficient platforms with strong processing power but also have the advantages of distributed computing systems balancing the workload between cores, processors, and nodes. This paper employs a 48‐node cluster infrastructure based on the Xilinx Zynq SoC to accelerate classical cryptographic algorithms, including hash functions, AES, and RSA. In this design, we leverage the flexibility of the software to implement node‐to‐node communication through the message passing interface (MPI), and we offload the compute‐intensive tasks to the FPGA to accelerate complex calculations with the parallelizability of specific reconfigurable coprocessors. In addition, we study several parallel cryptography optimizations based on FPGA to evaluate this cluster. Finally, using a comparison with a multi‐core desktop (Intel i7‐3770) and a many‐core server (288 cores), the efficiency of the implementations of the selected data encryption and decryption algorithms is presented to illustrate the performance of our system; we also gain up to 3.6× increase in energy efficiency.

Foreword to the Special Issue of the 8th International Conference on Applications and Techniques for Information Security (ATIS 2017)

“…The hybrid architecture–based clusters, which involve ARM CPUs and FPGA fabric, are playing an essential role in accelerating the encryption/decryption of massive data. The paper “A hybrid ARM‐FPGA cluster for cryptographic algorithm acceleration” employed a 48‐node cluster infrastructure based on the Xilinx Zynq SoC to accelerate classical cryptographic algorithms, including hash functions, AES, and RSA . During the design, the authors leveraged the flexibility of the software to implement node‐to‐node communication through the Message Passing Interface (MPI) and offloaded the compute‐intensive tasks to the FPGA to accelerate complex calculations with the parallelizability of specific reconfigurable coprocessors.…”