A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs

Abstract

SUMMARYThis paper presents an integrated approach of simulated annealing (SA) and genetic algorithm (GA) for the analogue module placement in mixed-signal integrated circuit layout designs. The proposed algorithm follows the optimization ow of a normal GA controlled by the methodology of SA. The bitmatrix chromosomal representation is employed to describe the location and the orientation of modules. Compared with the conventional bit-string representation, the proposed chromosomal representation tends to signiÿcantly improve the search e ciency. In addition, a slide-based at scheme is developed to transform an absolute co-ordinate placement of modules to a relative placement. In this way, the symmetry constraints imposed on analogue very large scale integration circuits can be easily fulÿlled in the placement run. Use of a radiation-decoder can also drastically shrink the conÿguration space without degrading search opportunities. The proposed algorithm has been tested with several example circuits. The experiments show this promising algorithm makes the better performance than the simpler SA or GA approaches working alone, and the quality of the automatically generated layouts is comparable to those done manually.

Mathematical methods for physical layout of printed circuit boards: an overview

“…Consequently, practically every known heuristic scheme, including cluster development (Areibi and Yang 2004;Hanan and Kurtzberg 1972a;Hanan et al 1976a;Magnuson 1977;Cox and Carroll 1980), knowledge based systems (Pannérec 2003), randomized local search algorithms such as simulated annealing (Sechen and Sangiovanni-Vincentelli 1986;Sechen 1988;Wong et al 1988;Wang et al 2000;Murata et al 1998), and genetic algorithms (Cohoon and Paris 1987;Shahookar and Mazumder 1990;Valenzuela and Wang 2002;Sait et al 2005;Areibi and Yang 2004), as well as combinations of these approaches (Zhang et al 2005) have been used to compute placements. Often, computed placements are improved by iterative heuristics based on component interchange (Magnuson 1977;Coté and Patel 1980).…”

Symmetry‐aware placement algorithm using transitive closure graph representation for analog integrated circuits

“…The early analog layout systems, such as [4][5][6], applied absolute placement approaches using the absolute-coordinate representation. To shrink the search solution space, a slide post-processing stage was proposed in [20] to convert absolute placement to relative placement. In contrast, to directly use relative placement methods, Balasa and Lampaert [7] explored the SP representation in the context of symmetry placement for analog layout design.…”

Efficient optimization‐oriented design methodology of high‐order 3‐D filters using 2‐D and 3‐D electromagnetic simulators

“…The 3‐D EM simulators are very accurate for the analysis of 3‐D structures, but they require high computational time and memory resources. The optimization techniques are usually classified as local (typically gradient‐based) or global (typically evolutionary) algorithms and are widely used in diverse applications such as image processing , passive and digital filter designs and for integrated circuit layout designs . In the RF/microwave field, the efforts are also focused on reducing the iteration number of those analysis tools requiring large computational times.…”