Accurate and computationally-efficient real-time simulation plays a key role in rapid control prototyping (RCP) of VSC-HVDC converters for their reliable operations in power grids. Hardware-in-theloop (HIL) based converter controller designs can be facilitated by real-time simulation to achieve the desirable responses of controller throughout all operating conditions. Although common for modular multilevel converters (MMCs), the real-time simulation approach has been scarcely applied to the new class of hybrid cascaded multilevel converters (HCMCs). In this paper, a computationally-efficient and accurate universal equivalent model (UEM) is proposed for a wide range of HCMC topologies, based on CPU and field-programmable gate array (FPGA) co-simulation. The hybrid five-level converter (H5LC), a novel DCfault tolerant, compact, and efficient VSC in the family of HCMCs, is used to derive the proposed UEM. The UEM utilizes CPUs to simulate the main circuits and controls of the main converter and employs an FPGA for calculation of the instantaneous voltage of very large number of full-bridge submodules (FBSMs), flying capacitors, and DC-side pole capacitors. Moreover, the FBSMs' voltage-balancing and switching algorithms are also implemented on FPGA. The proposed real-time CPU/FPGA-based H5LC-UEM is compared to the offline CPU-based detailed equivalent model to verify the new model and its numerical accuracy.INDEX TERMS FPGA, hybrid multilevel converter, modular multilevel converter (MMC), rapid control prototyping (RCP), real-time simulation, voltage-source converter high voltage direct current (VSC -HVDC).