A hybrid flash translation layer design for SLC–MLC flash memory based multibank solid state disk

Park, Jung–Wook; Park, Seung-Ho; Weems, Charles C.; Kim, Shin-Dug

doi:10.1016/j.micpro.2010.08.001

Cited by 21 publications

(28 citation statements)

References 6 publications

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“…In this paper, we propose a PRAM-based block updating management scheme, called as a PRAM updating SSD (PUSSD). This scheme employs PRAM to improve the original hybrid NAND flash SSD which is constructed as a combination of single-level cell (SLC) NAND flash and multi-level cell (MLC) NAND flash memories [6]. Through simulations, we have verified that the PUSSD scheme can provide higher write performance and longer lifetime in comparison with previous scheme.…”

Section: Introductionmentioning

confidence: 94%

“…For this reason, most SSD designs use a mapping technique to handle logical address to physical address translation and require the overall physical NAND flash space to be separated into logical data area and update area which can avoid performance overhead caused by frequent erase operations [5]. An example of this design is the hybrid flash translation layer (HFTL) scheme [6]. The HFTL uses a superblock policy to organize NAND flash memory blocks.…”

Section: Related Workmentioning

confidence: 99%

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A PRAM based block updating management for hybrid solid state disk

Lü

Choi

et al. 2012

IEICE Electron. Express

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Abstract:The goal of this research is to design a PRAM-based SSD (solid state disk) updating management scheme which uses PRAM for main logging area of previous hybrid SSDs. Specifically the proposed scheme can provide higher performance and longer lifetime than those of previous scheme. Simulation results show that overall write performance can be enhanced by around 380% on average and the lifetime of SSD can be increased by up to 6.5 times.

show abstract

Section: Introductionmentioning

confidence: 94%

Section: Related Workmentioning

confidence: 99%

A PRAM based block updating management for hybrid solid state disk

Lü

Choi

et al. 2012

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

show abstract

“…These SSD designs use a garbage collection mechanism to recycle the most useless updated area to supply the hot region in order to maintain a continually running SSD. An example of this design is the Hybrid Flash Translation Layer (HFTL) scheme [9]. The scheme of HFTL uses superblock policy to organize NAND flash blocks, which uses multiple NAND flash controllers to control multi-chips containing multi-blocks.…”

Section: Related Workmentioning

confidence: 99%

“…DRAM buffer will be used for MLC merge operation. The hybrid of SLC and MLC flash memory is designed and managed based on the superblock configuration [9]. The write requests, which include logical sector address and length, come from the host interface.…”

Section: Ph-ssd Architecturementioning

confidence: 99%

An Effective Hierarchical PRAM-SLC-MLC Hybrid Solid State Disk

Lü

Choi

et al. 2012

2012 IEEE/ACIS 11th International Conference on Computer and Information Science

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Currently, SLC-MLC hybrid SSD (solid state disk) products become mature. Phase-change random access memory (PRAM) is one of the new non-volatile memory materials used to enhance the limitation of original SLC-MLC hybrid SSD. Through reorganizing the basic functional modes among SLC, MLC, and PRAM, we proposed a new hybrid SSD architecture named PRAM-SLC-MLC Hybrid SSD (PH-SSD), in which a hierarchical updating method is designed. The PH-SSD employs PRAM as a primary updating area, uses SLC as a secondary updating area, uses MLC for main data storage, and performs data migration via a small capacity DRAM. Based on this proper arrangement, the PH-SSD can improve write performance and lifetime of SSD significantly. Through simulation, the PH-SSD achieves over 240% speedup and prolongs the lifetime by up to 2-3 times compared with the previous architecture.

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“…Moreover, there is an ongoing research on its use as a storage device in desktop computers [1]. Nonvolatile memory can be divided into two categories: NAND-and NOR-type flash memory.…”

Section: Introductionmentioning

confidence: 99%

Instruction and Data NAND Flash Memory System for Embedded Systems

Kim

Lee

2012

2012 International Conference on Information Science and Applications

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Harvard architecture uses physically separate memories for their instructions and data. In the case of a flash memory with a buffer system, separate data and instruction buffers can lead to diversification of a flash architecture and achieve the high performance by overcoming effectively the limitations of a unified buffer. So, the proposed NAND flash system is composed of two separate buffers for exploiting the characteristics inherent in each module. Also, we propose a new operating mechanism for reducing overhead of flash memory, that is, erase and write operations. According to our simulation results, the write operations and the erase operations are about 60% and 68% less than other unified buffer systems with two times more space, respectively. And also, the average memory access tine is improved by about 70% compared with other unified buffer systems.

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A hybrid flash translation layer design for SLC–MLC flash memory based multibank solid state disk

Cited by 21 publications

References 6 publications

A PRAM based block updating management for hybrid solid state disk

A PRAM based block updating management for hybrid solid state disk

An Effective Hierarchical PRAM-SLC-MLC Hybrid Solid State Disk

Instruction and Data NAND Flash Memory System for Embedded Systems

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