A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation

Xu, Ni; Rhee, Woogeun; Wang, Zhihua

doi:10.1109/jssc.2014.2345021

Cited by 32 publications

(11 citation statements)

References 22 publications

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“…However, the gain mismatch can be calibrated by digital compensation as shown in the recent two-point modulation SSCG with the BBPD [15], the DCO nonlinearity could be problematic. Since the frequency deviation of the SSCG is not high compared to the output frequency, the use of the separate FIRembedded 1-bit DS modulation only for the high-pass modulation path can be considered as a future work [16]. In this design, the initial DCO gain mismatch calibration is manually done by the field programmable gated array (FPGA).…”

Section: Sscg With Two-point Modulationmentioning

confidence: 99%

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A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

Xu¹,

Shen²,

Lv³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper describes a spread-spectrum clock generation method by utilizing a DS digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order DS modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The DS DPLL employs a twopoint modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 GHz spread-spectrum clock generator (SSCG) is implemented in 65 nm CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 dB and 11 dB with 10 kHz and 100 kHz resolution bandwidths respectively, consuming 6.34 mW from a 1 V supply.

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Section: Sscg With Two-point Modulationmentioning

confidence: 99%

“…The DLL suppresses the periodic jitter by the 30 kHz modulation and generates the multi-phase signals to the coarse-tracking phase rotator. The selected two phases become two-level reference phase for the 1-bit DS TDC that performs the fine phase tracking with oversampling [14][15][16][17]. Fig.…”

Section: Sscg With Two-point Modulationmentioning

confidence: 99%

A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

Xu¹,

Shen²,

Lv³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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“…5 shows a simplified block diagram of the proposed two-point modulator. Compared with the 1-bit high-pass modulation architecture [6], the proposed architecture has a multi-level quantizer with additional logic control block. The signal in the high-pass modulation generates a 2-bit output from a 20-bit input.…”

Section: Architecturementioning

confidence: 99%

“…2 [6]. Since the 1-bit high-pass modulation causes substantial quantization noise with a large size of varactor, a finiteresponse filter (FIR) method is also used to suppress the quantization noise.…”

Section: Introductionmentioning

confidence: 99%

“…Even though the multi-bit approach brings the nonlinearity problem back, the use of only a few bits with a separate high-pass modulation path greatly simplifies the nonlinearity calibration procedure. A semi-digital PLL without the time-to-digital converter (TDC) is designed based 978-1-4799-8391-9/15/$31.00 ©2015 IEEE on [6], but the proposed method can be also useful for any ADPLL-based two-point modulator.…”

Section: Introductionmentioning

confidence: 99%

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A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path

Rhee

Wen

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper describes an effective way of relaxing the nonlinearity problem of the digitally-controlled oscillator (DCO) in the two-point modulator design. A separate coarse varactor array dedicated for the high-pass modulation significantly simplifies the nonlinearity calibration of the DCO with a few-bit control. In addition, a finite-impulse response (FIR) filter is designed for the multi-bit high-pass modulation path to reduce the quantization noise, while offering a time-interleaving operation to minimize the DCO sensitivity to the coupling during switching time. A two-point modulator based on a semidigital fractional-N phase-locked loop (PLL) is implemented in 0.18μm CMOS. Simulation results show that the proposed modulator can achieve 10Mb/s GFSK/GMSK modulations with the EVM of -37dB.

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Digital‐IntensivePLL

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A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation

Cited by 32 publications

References 22 publications

A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path

Digital‐IntensivePLL

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