A Hybrid Multiplier Architecture Using Partially Redundant Booth Algorithm

Abstract

In the conventional hybrid Booth multiplier architecture, the reduction of the radix-8 partial products begins after the generation of three times the multiplicand has been performed by a wide bit widths adder in parallel with the reduction of the radix-4 partial products. Thus, the reduction process is not as time efficient. To solve this problem, we propose a novel hybrid multiplier architecture utilizing partially redundant radix-8 Booth encoding to generate three times the multiplicand. Experiments show that this novel hybrid multiplier architecture requires 2.8% smaller area and 4.2% less power with the almost same delay for a 64x64-bit multiplier as compared with a radix-4 implementation. The novel hybrid radix-4/radix-8 architecture is therefore a compromise between high speed and low power.