“…The multi-mode LINC PA was capable of enhancing its linear output power by 7% and its efficiency by 8% compared to the conventional method. H. Lee et al (2013) also presented a hybrid polar-LINC PA that employed a combination of polar and LINC mechanisms [ 124 ]. This hybrid polar-LINC PA was configured in a differential structure comprising two pairs of driver stages and power stages and an output combiner.…”
Wireless communication systems have undergone significant development in recent years, particularly with the transition from fourth generation (4G) to fifth generation (5G). As the number of wireless devices and mobile data usage increase, there is a growing need for enhancements and upgrades to the current wireless communication systems. CMOS transceivers are increasingly being explored to meet the requirements of the latest wireless communication protocols and applications while achieving the goal of system-on-chip (SoC). The radio frequency power amplifier (RFPA) in a CMOS transmitter plays a crucial role in amplifying RF signals and transmitting them from the antenna. This state-of-the-art review paper presents a concise discussion of the performance metrics that are important for designing a CMOS PA, followed by an overview of the trending research on CMOS PA techniques that focuses on efficiency, linearity, and bandwidth enhancement.
“…The multi-mode LINC PA was capable of enhancing its linear output power by 7% and its efficiency by 8% compared to the conventional method. H. Lee et al (2013) also presented a hybrid polar-LINC PA that employed a combination of polar and LINC mechanisms [ 124 ]. This hybrid polar-LINC PA was configured in a differential structure comprising two pairs of driver stages and power stages and an output combiner.…”
Wireless communication systems have undergone significant development in recent years, particularly with the transition from fourth generation (4G) to fifth generation (5G). As the number of wireless devices and mobile data usage increase, there is a growing need for enhancements and upgrades to the current wireless communication systems. CMOS transceivers are increasingly being explored to meet the requirements of the latest wireless communication protocols and applications while achieving the goal of system-on-chip (SoC). The radio frequency power amplifier (RFPA) in a CMOS transmitter plays a crucial role in amplifying RF signals and transmitting them from the antenna. This state-of-the-art review paper presents a concise discussion of the performance metrics that are important for designing a CMOS PA, followed by an overview of the trending research on CMOS PA techniques that focuses on efficiency, linearity, and bandwidth enhancement.
“…It enables efficient and digital-intensive implementation, but faces the problem of needing to reproduce very narrow pulses in the PA output. In addition, some more experimental architectures have been proposed, including hybrids between Cartesian and polar transmitters [96], or between polar and outphasing transmitters [97], both of which ease the bandwidth requirements of polar modulation by combining it with other methods. Mixed-mode outphasing, which is distinct from outphasing as previously described due to the use of amplitude modulation in the two signal paths, has been explored primarily in analog PAs implemented with discrete components and passive elements [98,99].…”
“…Many groups have studied techniques to improve the efficiency of linear PAs with large BOP. For example, envelope tracking techniques [1], [2], polar modulation techniques [3], [4], and Doherty architectures [5]- [8] have been proposed. A Doherty PA (DPA), which consists of main and auxiliary amplifiers, uses load modulation to improve efficiency at BOP.…”
A fully integrated transformer-based quasi-Doherty power amplifier (DPA) with an adaptive power divider (APD) is presented in this paper. A novel folded combining transformer is designed for power combining, which has smaller insertion loss than a conventional one. An APD adaptively controls the power delivered to carrier and peaking amplifiers by altering the input impedance of the peaking amplifier, which has a variable resonance frequency that changes according to the input power. Most of the power is delivered to the carrier amplifier at low incoming power, and it is divided between the carrier and the peaking amplifiers at high incoming power. With continuous wave signal at 1850 MHz, the quasi-DPA implemented with an SOI CMOS process achieves 39.8% and 44.4% power-added efficiencies (PAEs) at the first and the second peak, respectively. With wideband code division multiple access signal, it has 29.2-dBm average linear output power and a 40.47% PAE with a −33-dBc adjacent channel leakage ratio 1. With long-term evolution (LTE) signal, it delivers 27.2-dBm average linear output power and a 37.7% PAE, satisfying linearity requirements for the LTE.
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