2020
DOI: 10.1002/2050-7038.12535
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A hybrid space vector modulation for the near‐zero common‐mode voltage and common‐mode current mitigation in diode‐clamped multilevel‐inverter‐fed induction motor drive

Abstract: Three-level diode-clamped (DC) multilevel inverters (MLIs) and its pulse width modulations (PWMs) are studied widely due to its extensive rewards in industrial drives. These modulation schemes are mainly concentrated to mitigate the zero common-mode (CM) voltage (CMV) and CM current (CMC). Unfortunately, although achieving near-zero CMV, these conventional methods are inadequate to maintain the DC-link low-frequency neutral point voltage oscillations. Hence, bulky DC-link capacitors are used in DC-MLIs. In thi… Show more

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Cited by 9 publications
(3 citation statements)
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“…Since the zero state is avoided, CMV is reduced to ±Vdc/6. [94] Three nearest medium vectors (M 3 V)…”
Section: Redundant Vectors Are Removedmentioning
confidence: 99%
See 1 more Smart Citation
“…Since the zero state is avoided, CMV is reduced to ±Vdc/6. [94] Three nearest medium vectors (M 3 V)…”
Section: Redundant Vectors Are Removedmentioning
confidence: 99%
“…The CMV is controlled by eliminating some of the vectors which produces CMV. The utilization of one zero vector "ooo" and medium vector for generating the switching sequence will completely eliminate the CMV [86] - [94]. The partial elimination of CMV also possible with modification of SVM techniques.…”
Section: Open End Winding Five Phase Inverter: Figure 64 Five Phase Open End Winding Topologymentioning
confidence: 99%
“…Therefore, random bit number generations need higher circuit cost and implementation burden. Hence, the researchers recommended a linear feedback shift register (LFSR) for getting more randomness [35][36][37][38][39]. LFSR is commonly referred to as a pseudo-PWM code generator and works using a digital logical process of a binary number [29].…”
Section: Introductionmentioning
confidence: 99%