A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications

Santoro, Francesco; Kuhn, R.; Gibson, N.; Rasera, Nicola; Tost, T.; Graeb, Helmut; Wicht, Bernhard; Brederlow, R.

doi:10.1109/jssc.2018.2799964

Cited by 34 publications

(10 citation statements)

References 16 publications

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“…Our proposed specification and performance are summarized in Table 1. It clearly shows that the proposed TFCS and ALCS technique yields an improvement in the power efficiency (4~6%) compared to some of the latest state-of-the-art research work [17][18][19]. However, one drawback is the fact that the external inductor and capacitor are relatively larger in our proposed work so as to achieve a smaller peak-to-peak output voltage ripple for a more accurate sensing of the load current.…”

Section: Resultsmentioning

confidence: 82%

Designing a Twin Frequency Control DC-DC Buck Converter Using Accurate Load Current Sensing Technique

Kok,

Siek

2023

Electronics

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In this paper, a buck DC-DC converter with the proposed twin frequency control scheme (TFCS) and accurate load current sensing (ALCS) was designed and implemented with 0.18 µm CMOS technology for a supply voltage ranging from 2.0 to 3.0 V, which is compatible with state-of-the-art batteries (NiCd/NiMH: 1.1–2 V, Li-Ion: 2.5–4.2 V). The proposed converter yields a peak efficiency of about 92.7% with a load current of 30 mA. Furthermore, it only occupies a silicon area of 1.3 mm2. The proposed buck converter is dedicated for smartphone applications whereby it spends most of its time in idle, low load conditions.

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Section: Resultsmentioning

confidence: 82%

Designing a Twin Frequency Control DC-DC Buck Converter Using Accurate Load Current Sensing Technique

Kok,

Siek

2023

Electronics

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“…In the next sub-section, the proposed work will be presented and analyzed in greater detail. At the same time, there are other DC-DC converters which can provide a wide load range with good efficiency while consuming very low quiescent current, which will no doubt be the major power consumption in sensing or low-load mode [63][64][65][66][67][68][69][70].…”

Section: Voltage Level Shiftermentioning

confidence: 99%

A DC-DC Converter with Switched-Capacitor Delay Deadtime Controller and Enhanced Unbalanced-Input Pair Zero-Current Detector to Boost Power Efficiency

Kok,

Tang,

Teo

et al. 2024

Electronics

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This proposed work introduces a DC-DC converter with Switched-Capacitor Delay Deadtime Controller (SCD-DTC), Digitally Controlled Start-Up Block (DC-SUB), and Enhanced Unbalanced-Input Pair Zero-Current Detector (EUIP-ZCD) that helps to improve the overall power efficiency. It also introduces the discussion of key signal waveforms and the two major optimization flowcharts. This proposed DC-DC converter can simultaneously achieve optimized deadtime (body diode conduction < 3 ns) and almost fully eliminate the phenomenon of reverse inductor current (RIC). Furthermore, it also shows that it can achieve a well-regulated output voltage of 1.8 V with <0.01% of output ripple riding on it. All the post-layout simulation results are carried out using 0.18 µm 1P6M CMOS process using Cadence Virtuoso Spectre Circuit Simulator. The silicon chip area of our proposed work (including the output pad frame) is 1.44 mm2. The chip fabrication was sent out in January 2024 and the return of the measurement dies is expected in March 2024. The post-layout simulation results will no doubt closely resemble the measurement results since the proposed work is mostly controlled by digital blocks.

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“…In recent years, different methods have been proposed to reduce the power consumption of DC-DC converter and ensure its high efficiency [16][17][18][19][20]. Under heavy load and medium load conditions, pulse width modulation (PWM) is often used, while in light load mode is adopted different control strategies.…”

Section: Introductionmentioning

confidence: 99%

An ultra‐low quiescent current tri‐mode DC–DC boost converter with 95.6% peak efficiency for internet of things application

Zheng

Song

Guo

et al. 2023

IET Power Electronics

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An ultra‐low quiescent current tri‐mode DC–DC boost converter is proposed in this paper, which can efficiently handle loads from 1 μA to 300 mA, providing 5‐V output from 3 to 4.2‐V input. Hysteresis current mode control is adopted to realize seamless mode switching between continuous conduction mode (CCM) and discontinuous conduction mode (DCM). In order to deal with the light load situation, this paper proposes a quasi burst mode (QBM). In this mode, most of the modules are turned off and only the QBM controller, low‐power current bias and sample and hold circuit are retained, which significantly reduces the static current of the converter, and thus improves the light load efficiency. Meanwhile, the average current of error amplifier and comparator are reduced significantly by dynamic biasing. Finally, the efficiency of the converter is greatly improved and kept at a reasonable output ripple. The proposed converter is implemented in a 0.13‐μm BCD process design and manufacturing. The test results show that the quiescent current of the converter is only 780 nA, which can achieve a peak efficiency of 95.6%, and ensure that the efficiency is maintained above 80% in the load range of 10 μA to 300 mA.

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A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications

Cited by 34 publications

References 16 publications

Designing a Twin Frequency Control DC-DC Buck Converter Using Accurate Load Current Sensing Technique

Designing a Twin Frequency Control DC-DC Buck Converter Using Accurate Load Current Sensing Technique

A DC-DC Converter with Switched-Capacitor Delay Deadtime Controller and Enhanced Unbalanced-Input Pair Zero-Current Detector to Boost Power Efficiency

An ultra‐low quiescent current tri‐mode DC–DC boost converter with 95.6% peak efficiency for internet of things application

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