A Q-Learning-Based Fault-Tolerant and Congestion-Aware Adaptive Routing Algorithm for Networks-on-Chip

Liu, Yi; Guo, Rujia; Xu, Changqing; Weng, Xiaodong; Yang, Yintang

doi:10.1109/les.2022.3176233

Cited by 6 publications

(2 citation statements)

References 11 publications

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“…The programmable structure is a reconfigurable MPSoC solution that permits online configuration and guarantees that minute faults do not affect system performance. Mesh NoC is scalable and based on XY routing [22]. When comparing the two, the ring NoC has wider coverage.…”

Section: Related Workmentioning

confidence: 99%

2D router chip design, analysis, and simulation for effective communication

Agarwal

Garg

Kumar

2023

IJ-ICT

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The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.

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Section: Related Workmentioning

confidence: 99%

2D router chip design, analysis, and simulation for effective communication

Agarwal

Garg

Kumar

2023

IJ-ICT

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“…Ref. Liu et al [13] proposed QFCAR-W routing algorithm, which is inspired by the NoC fault-tolerant Q-learning technique.…”

Section: Introductionmentioning

confidence: 99%

TTQR: A Traffic- and Thermal-Aware Q-Routing for 3D Network-on-Chip

Liu

Chen

Zhao

et al. 2022

Sensors

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The die-stacking structure of 3D network-on-chips (3D NoC) leads to high power density and unequal thermal conductance between different layers, which results in low reliability and performance degradation of 3D NoCs. Congestion-aware adaptive routing, which is capable of balancing the network’s traffic load, can alleviate congestion and thermal problems so as to improve the performance of the network. In this study, we propose a traffic- and thermal-aware Q-routing algorithm (TTQR) based on Q-learning, a reinforcement learning method. The proposed algorithm saves the local traffic status and the global temperature information to the Q1-table and Q2-table, respectively. The values of two tables are updated by the packet header and saved in a small size, which saves the hardware overhead. Based on the ratio of the Q1-value to the Q2-value corresponding to each direction, the packet’s output port is selected. As a result, packets are transferred to the chosen path to alleviate thermal problems and achieve more balanced inter-layer traffic. Through the Access Noxim simulation platform, we compare the proposed routing algorithm with the TAAR routing algorithm. According to experimental results using synthetic traffic patterns, our proposed methods outperform the TAAR routing algorithm by an average of 63.6% and 41.4% in average latency and throughput, respectively.

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