A jitter equalization technique for minimizing supply noise induced jitter in high speed serial links

Abstract

As data rate of serial interface has increased dramatically, timing margin has gotten tighter and tighter. Supply voltage has also kept deducing according to silicon process technology. However, supply noise is hardly reduced due to higher data rate, a huge number of transistors and slower improvement of packaging technology. Therefore, the jitter due to supply noise can be quite large compared to other jitter components. The jitter due to supply noise is not cancelled out by CDR or PLL at the receiver since PDN resonance frequency is higher than loop bandwidth of CDR or PLL. It is not cost effective if only PDN improvement is adopted to reduce supply noise induced jitter. It is essential to optimize performance at architecture level including circuits and PDN. In this paper, the new technique is proposed to minimize supply noise induced jitter in high speed serial interface. The proposed techniques called Jitter Equalizer (JEqualizer) improves jitter performance by 80% with minimal power increase and area over head. The impact is evaluated by supply noise induced jitter modeling.

Reduction of Power Supply Induced Jitter with Applications to DDR Controllers

“…Mainly the package inductance induces undesired voltage fluctuation, ΔV, through the mechanism of ) / ( dt di L V = ∆ [3], so that the current transients on the PDN cause power supply noise. To solve this issue, in the past few years many studies on power supply induced jitter (PSIJ) have been published [4][5][6][7][8][9][10].…”

“…As transmission speed surpasses multi-gigabits per second for I/O interfaces, to meet the stringent timing budget, power supply induced jitter has attracted many research efforts [4][5][6][7][8][9][10] in the past few years. For power supply induced jitter (PSIJ) prediction, the conventional alpha method [21] is too pessimistic; the most accurate method is proposed in [23] where circuit simulation extracts the power supply induced jitter sensitivity (PSIJS)…”

Power Supply Induced Jitter Including the Ground Bounce and Transmission Media Effects

“…Equalization techniques based on jitter sensitivity and jitter reduction via architectural level changes were addressed in [28]. The effect of a silicon interposer channel and paths of noise via different transfer functions can be found in [29].…”