A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces

Ichiyama, K.; Kusaka, Takashi; Ishida, M.

doi:10.1109/itc44170.2019.9000138

Cited by 3 publications

(2 citation statements)

References 5 publications

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“…Software debugging and electrical and logic validation make up the bulk of the post-silicon validation process. In silicon validation [7], testing the chip's efficiency at a set speed under varying operating circumstances is of utmost importance. Neglecting to consider the efficiency of the chip might result in disastrous failure in real-time applications.…”

Section: A Perspective On the Evolution Of Analog Bench Validation An...mentioning

confidence: 99%

Advances in Traditional Electrical Validation of High-Speed Serial Connections Using Innovative Debugging Methods and Machine Learning Models.

Mohammad Ahmar Khan

2024

jes

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As technology continues to shrink and more heterogeneous blocks are combined into single System on a chip (SOCs), the design of high-performance integrated circuits is getting more and more difficult. In the course of silicon validation, which includes testing (Wafer Testing, Automatic Test Equipment), digital validation (Functional Data route, FSM), analogue bench validation (Electrical, Interoperability), and system validation, a number of challenges that arise from the complicated design are uncovered. The process, methods, and constraints of each domain are unique. Electrical problems that have already passed through earlier stages of design are the primary focus of analogue validation. The analogue signal or mix signal nature of IPs makes it impossible for digital validation or any of the other post-silicon domains to discover electrical flaws on its own. As a result, studies focusing on analogue bench validation have grown in prominence. Recent developments in analogue bench validation, focusing on high-speed serial interface in particular, are highlighted in the proposed study. In addition, this article summarises recent technological developments that provide avenues for further study regarding analogue bench validation.

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Section: A Perspective On the Evolution Of Analog Bench Validation An...mentioning

confidence: 99%

Advances in Traditional Electrical Validation of High-Speed Serial Connections Using Innovative Debugging Methods and Machine Learning Models.

Mohammad Ahmar Khan

2024

jes

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“…High-speed serial interface devices are becoming widely used in communications, ranging from embedded to high-performance systems, as well as from on-chip and massive haul [18]. Due to the need for high-speed data processing, the data transmission speed of these interfaces has been steadily increasing [19,20]. Although, in the past, the parallel approach was the most commonly used for high-speed communication, this is no longer the case.…”

Section: High-speed Interface Overview and Related Workmentioning

confidence: 99%

A Novel Framework for Testing High-Speed Serial Interfaces in Multiprocessor Based Real-Time Embedded System

et al. 2021

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Recent years has seen a tremendous increase in processing requirements of present-day embedded system applications. Embedded systems consist of multiple processing elements (PEs) connected to each other using different types of interfaces. Many complicated tasks are accomplished by embedded systems in varied settings, which may introduce errors during inter-processor communication. Testing such systems is tremendously difficult and challenging from testing non-real time systems. A major part of testing real time embedded systems involves ensuring accuracy and timing in synchronous inter-process communication More specifically, the synchronization and inter-processor communication of real-time applications makes testing a challenging task and due to the demand for higher data rate increases, day-by-day, making testing of such systems even more complex. This paper presents a novel frame work that uses multiple instances of simulators with physical high-speed serial interfaces to emulate any real time embedded system communication. The framework presents a testing technique that detects all faults related to synchronization of high-speed synchronous serial interfaces in a systematic manner. The novelty of our approach is to simulate communication across multiple processors in a simulation environment for detecting and localizing bugs. We verify this framework using a case study consisting of an embedded software defined radio (SDR) system. The test results show the applicability of our approach in fixing bugs that relates to synchronization issues that otherwise are very hard to find and fix in very complicated systems, such as SDR.

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Cost-Effective Test Method for screening out Unexpected Failure in High Speed Serial Interface IPs

Ahn

Seo

Kim

et al. 2020

2020 IEEE International Test Conference (ITC)

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A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces

Cited by 3 publications

References 5 publications

Advances in Traditional Electrical Validation of High-Speed Serial Connections Using Innovative Debugging Methods and Machine Learning Models.

Advances in Traditional Electrical Validation of High-Speed Serial Connections Using Innovative Debugging Methods and Machine Learning Models.

A Novel Framework for Testing High-Speed Serial Interfaces in Multiprocessor Based Real-Time Embedded System

Cost-Effective Test Method for screening out Unexpected Failure in High Speed Serial Interface IPs

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