A Jittered-Sampling Correction Technique for ADCs

Tourabaly, J.; Osseiran, Adam

doi:10.1109/delta.2008.79

Cited by 6 publications

(4 citation statements)

References 27 publications

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“…Therefore, a special research direction has been derived to address the limitation of clock jitter on the development of high-resolution ADCs [6][7][8][9]. The clock jitter is compensated by the Taylor series in [6]. Literature [7] selects two sampling data segments with specific lengths and the same initial phase to extract background noise to reduce the overall clock jitter root-mean-square (RMS).…”

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confidence: 99%

“…Calibration mechanism with LSTM: Sampling clock jitter is a shortterm, non-cumulative variable that represents the time deviation between the actual timing position and the ideal position of the digital signal. More importantly, the clock jitter follows a Gaussian distribution with a zero-mean and is independent of the signal [6][7][8][9][10]. Based on the characteristics above, single-sample based calibration algorithms cannot deal with the random clock jitter.…”

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confidence: 99%

“…However, these methods rarely consider compensating the clock jitter because of its randomness. Therefore, a special research direction has been derived to address the limitation of clock jitter on the development of high-resolution ADCs [6][7][8][9]. The clock jitter is compensated by the Taylor series in [6].…”

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confidence: 99%

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An analog‐to‐digital converter calibration algorithm with clock jitter compensation based on bidirectional long‐short‐time‐memory

Zeng

Wan

Chen

et al. 2022

Electronics Letters

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This letter proposes a bidirectional long‐short‐time‐memory (bi‐LSTM)‐based analog‐to‐digital converter (ADC) background calibration method with a clock jitter compensation function. Different from traditional calibration algorithms, the proposed algorithm utilizes the sequence property of the signal by introducing an LSTM network. The network contains three parts, including a linear layer for input encoding, a refine layer for sequence processing, and a linear layer for output decoding. Two ADCs are used to train the network, one of which is the target to be calibrated, that is, a high‐speed high‐resolution ADC, and the other is a low‐speed ultra‐high‐resolution ADC producing the ideal signal. After the training stage, the network can be used as a postprocessor for the target ADC to compensate for the systemic errors and clock jitter, simultaneously. In the experiments, the proposed method is used to calibrate an ADC12D1600RFIUT, realizing the improvement of signal‐to‐noise distortion ratio (SNDR) from 43.41 to 66.82 dB and SFDR from 56.95 to 98.93 dB.

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An analog‐to‐digital converter calibration algorithm with clock jitter compensation based on bidirectional long‐short‐time‐memory

Zeng

Wan

Chen

et al. 2022

Electronics Letters

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“…While several results are available in the literature on jittered sampling [6], [7] as well as on experimental measurements and instruments performance [3], [5], [8], [9], an analytical methodology for the performance study of the AD/DA conversion is still missing.…”

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Signal Reconstruction Errors in Jittered Sampling

Nordio

Chiasserini

Viterbo

2009

IEEE Trans. Signal Process.

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Abstract-One of the most significant types of error in digital signal processing (DSP) systems working with wideband signals is the error introduced by the analog-to-digital (AD) and digital-to-analog (DA) converters. This paper presents an accurate and simple method to evaluate the performance of AD/DA converters affected by clock jitter, which is based on the analysis of the mean square error (MSE) between the reconstructed signal and the original one. Using an approximation of the linear minimum MSE (LMMSE) filter as reconstruction technique, we derive analytic expressions of the MSE. In particular, through asymptotic analysis, we are able to simply evaluate the performance of digital signal reconstruction as a function of the clock jitter, number of quantization bits, signal bandwidth and sampling rate.

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