A Josephson built-in self-testing (JBIST) system for gigahertz functional tests of Josephson RAMs

Abstract

We propose a Josephson built-in self-testing (JBIST) system. The aim of the JBIST system is to perform functional tests for Josephson RAMs at more than 1 GHz. The prototype JBIST circuit is designed for a 256 bit Josephson RAM, and consists of an instruction ROM and a processing circuit. A MARCHING test program is written into the instruction ROM, and the processing circuit executes the program on the instruction ROM. Total power consumption of the JBIST circuit is designed to be 4.2 mW. Estimated delays for the critical paths suggest the potential of a gigahertz clock testing. We fabricated the JBIST circuit chips by using Nb-AlO x -Nb Josephson junctions. The component circuits in the JBIST circuit (sequence controller, comparator, and instruction ROM) are successfully operated.

Progress in Nb-based low-temperature superconductive electronics for high-speed digital applications in Japan

“…Memory chips by Josephson device technology have reached the 4 kbit integration level [6,13]. Recent progress makes possible high bit yield of the chip and high access speed [14][15][16]. Very recently, a new memory cell design and its operation have been announced paving the way toward a 16 kbit Josephson RAM.…”