A junctionless dual-gate MOSFET-based programmable inverter for secured hardware applications using nitride charge trapping

Abstract

In this paper, we have investigated a junction-less dual gate MOSFET (JL-DG-MOSFET) based programmable inverter considering oxide-nitride-oxide (SiO2/Si3N4/SiO2) gate stack, which offers short/long term memory as well as logic functionalities depending on charge trapping in the nitride layer. It has been shown that the pulsing intervals play a pivotal role in deciding the STP (short term plasticity) /LTP (long term plasticity) window based on the charges trapped/de-trapped at/near the oxide/nitride interface. Moreover, we have demonstrated a JL-DG MOSFET- -based CMOS inverter with programmable switching threshold and propose a scheme for secure key generation for authentication. Intra-hamming distance among the 21 keys generated by the programmable inverter has been also depicted to demonstrate the efficacy of the proposed framework. This will eliminate the physical separation between the logic and memory and can offer attractive solutions to the silicon based low power neuromorphic computing and the hardware security.