A Language and Tool for Generating Efficient Virtual Machine Interpreters

Gregg, David; Ertl, M. Anton

doi:10.1007/978-3-540-25935-0_12

Cited by 6 publications

(5 citation statements)

References 16 publications

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“…Vmgen * 3 [8], [10] and its successor Tiger [3] are virtual machine interpreter generators with special support for stack machines. Interpreters of VMs such as Gforth [7] and Cacao Java VM [11] were described in Vmgen.…”

Section: Related Workmentioning

confidence: 99%

Generating Virtual Machine Code of JavaScript Engine for Embedded Systems

Hirasawa

Iwasaki

Ugawa

et al. 2022

Journal of Information Processing

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Virtual machines (VMs) for dynamically managed languages such as JavaScript are generally implemented in C or C++. Implementation of VMs in such low-level languages offers the advantage of high flexibility, but it suffers from problems of descriptiveness and safety. These problems are due to the fact that even though a variety of VM operations are based on the VM's internal datatypes for first-class objects in the target language, the C code typically treats all VM internal datatypes as a single type in C. In addition, VMs implemented in C or C++ have a size problem which is a serious issue for VMs on embedded systems. The reason for this problem is the difficulty of eliminating unnecessary code fragments from the C code for a specific application. To solve these problems, we propose a domain-specific language for describing VM programs and a corresponding compiler to C programs, called VMDL and VMDLC, respectively. We also propose related utility tools. This framework enables generation of C source code for an eJSVM, a JavaScript VM for embedded systems. VMDL's concise syntax enables static VM datatype analysis for optimizations and error detection. We evaluated the framework and confirmed its effectiveness from both qualitative and quantitative viewpoints.

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Section: Related Workmentioning

confidence: 99%

Generating Virtual Machine Code of JavaScript Engine for Embedded Systems

Hirasawa

Iwasaki

Ugawa

et al. 2022

Journal of Information Processing

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“…Testing and debugging Virtual Machines (VMs) is a laborious task without the proper tooling, which is aggravated when the VM targets multiple architectures [5]. To cope with the elevated cost of building language VMs, approaches such as VM generation frameworks [9,11,13,15,20,25,33], Metacircular VMs [28,31,32] and simulation-based VM generators [15,20,24,25] were created.…”

Section: Introduction and Problemmentioning

confidence: 99%

Differential testing of simulation-based VM generators

Misse-Chanabier

Polito

Ducasse

et al. 2022

Proceedings of the 37th ACM/SIGAPP Symposium on Applied Computing

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Testing and debugging language Virtual Machines (VMs) is a laborious task without the proper tooling. This complexity is aggravated when the VM targets multiple architectures. Simulation-based VM generator frameworks allow one to write test cases on the simulation, however they do not ensure the correctness of the generated artifact due to the semantic gap between the environments.In this article we propose Test Transmutation. It extends simulationbased VM generator frameworks to also generate simulation test cases and execute them on the generated VMs. It extends such frameworks to translate test cases and applies differential testing and non-semantic-preserving mutations. Test Transmutation detects bugs that are representative of typical VM modifications. Moreover, we apply it to a set of real test cases of the Pharo VM and find several issues. Our approach shows promising results to test simulation-based VM generator frameworks. CCS CONCEPTS• Software and its engineering Compilers; Software testing and debugging;

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“…On the other hand, many solutions focus on improving general interpreter behavior by minimizing branch miss-predictions of interpreter dispatches and stack caching. Solutions to branch mis-predictions propose variants of code threading [1,4,6,7,10] and improving it further with selective inlining [14]. Some solutions aim for minimizing branch miss-predictions by modifying the intermediate code (e.g., bytecode) design with super-instructions [15] and register-based instructions [9,16].…”

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confidence: 99%

Interpreter Register Autolocalisation: Improving the Performance of Efficient Interpreters

Polito¹,

Palumbo²,

Tesone³

et al. 2022

Companion Proceedings of the 6th International Conference on the Art, Science, and Engineering of Programming

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Language interpreters are generally slower than (JIT) compiled implementations because they trade off simplicity for performance and portability. However, they are still an important part of modern Virtual Machines (VMs) as part of mixed-mode execution schema. The reasons behind their importance are many. On the one hand, not all code gets hot and deserves to be optimized by JIT compilers. Examples of cold code are tests, command-line applications, and scripts. On the other hand, compilers are more difficult to write and maintain, thus interpreters are an attractive solution because of their simplicity and portability. In the context of this paper, we will center on bytecode interpreters.Interpreter performance has been a hot topic for a long time, where several solutions have been proposed with different ranges of complexity and portability. On the one hand, some work proposes to optimize language-specific features in interpreters such as type dispatches using static type predictions, quickening [3] or type specializations [18]. On the other hand, many solutions focus on improving general interpreter behavior by minimizing branch miss-predictions of interpreter dispatches and stack caching. Solutions to branch mis-predictions propose variants of code threading [1,4,6,7,10] and improving it further with selective inlining [14]. Some solutions aim for minimizing branch miss-predictions by modifying the intermediate code (e.g., bytecode) design with super-instructions [15] and register-based instructions [9,16]. Stack caching [5] proposes to optimize the access of operands by caching the top of the stack.interpreter registers are also related to stack caching: interpreter variables that are critical to the efficient execution of the interpreter loop. Examples of such variables are the instruction pointer (IP), the stack pointer (SP), and the frame pointer (FP). Interpreter registers put pressure on the overall design and implementation of the interpreter: Req1: Value access outside the interpreter loop. VM routines outside of the interpreter loop may require access to interpreter registers. For example, this is the case of garbage collectors that need to traverse the stack to find root objects, routines that unwind or reify the stack, or give access to stack values to native methods. Req2: Efficiency. Interpreter registers are used on each instruction to manipulate the instruction stream and the stack. Under-efficient implementations have negative impacts on performance.These two requirements are opposing in the sense that Req1 demands that register values are stored on globally accessible memory, either in the heap or the data sections of the process, while Req2 would benefit from putting those values in registers and avoid memory accesses at all.

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A Language and Tool for Generating Efficient Virtual Machine Interpreters

Cited by 6 publications

References 16 publications

Generating Virtual Machine Code of JavaScript Engine for Embedded Systems

Generating Virtual Machine Code of JavaScript Engine for Embedded Systems

Differential testing of simulation-based VM generators

Interpreter Register Autolocalisation: Improving the Performance of Efficient Interpreters

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