A large-vocabulary real-time continuous-speech recognition system

Murveit, Hy; Mankoski, J.; Rabaey, Jan M.; Brodersen, R.W.; Stoezle, T.; Chen, D.; Narayanaswamy, S.; Yu, Rong; Schrupp, P.; Schwartz, Richard; Santos, André Vinícius dos

doi:10.1109/icassp.1989.266546

Cited by 16 publications

(4 citation statements)

References 7 publications

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“…In BEAM [4], a shared bus architecture computer used by the SPHINX speech recognizerll91, bus contention problems are partly compensated for by having local cache memory for both data and instructions. Other architectures include processor trees [29], pipelines [6], SIMD [9,25] and dedicated hardware [24,26]. In each case the recognition algorithm is implemented using a synchronous methodology.…”

Section: Figure 1 Parsifal T-rack and Sun Host Computer Systemmentioning

confidence: 99%

‘Blade Runner’: A real‐time speech recognizer

Chong

Fallside

Marsland

et al. 1991

Concurrency: Pract. Exper.

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SUMMARYA real-time prototype speech recognizer has been implemented on a &-processor distributedmemory parallel computer. Simple phrases are recognized in approximately 4 to 10 seconds. Scalability, performance and flexibiiity are the three main aims of this implementation, the ultimate goal being to construct a large vocabulary speech recognizer whkh responds qukkly. A set of three techniques is investigated in this implementation: asynchronous methodology to minimize synchronization overheads, distributed control to avoid a central communications bottleneck, and dynamic load balancing to provide a flexible response to an unpredictable Computational load. The effect on memory, processor time allocation and communications is observed in real-time using hardware monitoring aids.

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Section: Figure 1 Parsifal T-rack and Sun Host Computer Systemmentioning

confidence: 99%

‘Blade Runner’: A real‐time speech recognizer

Chong

Fallside

Marsland

et al. 1991

Concurrency: Pract. Exper.

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“…"pruning" paths whose probabilities fall below a threshold [9]), but this is more difficult on parallel architectures than on serial ones [4]. Other approaches to parallel implementation include processor farms to automatically balance the load [1], [10], a more coarse-grained distributed computing model [3], [10], a tree-based architecture [9], or custom ICs with fine-grained PEs [7].…”

Section: Previous Implementationsmentioning

confidence: 99%

Reconfigurable Computing for Speech Recognition: Preliminary Findings

Melnikoff

James-Roxby

Quigley

et al. 2000

Lecture Notes in Computer Science

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Abstract. Continuous real-time speech recognition is a highly computationallydemanding task, but one which can take good advantage of a parallel processing system. To this end, we describe proposals for, and preliminary findings of, research in implementing in programmable logic the decoder part of a speech recognition system. Recognition via Viterbi decoding of Hidden Markov Models is outlined, along with details of current implementations, which aim to exploit properties of the algorithm that could make it well-suited for devices such as FPGAs. The question of how to deal with limited resources, by reconfiguration or otherwise, is also addressed.

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“…Although dedicated architectures are used, they suffer from hardware complexity and significant power consumption. Yet only a few VLSI architectures have been reported [4,6,7,8]. We proposed an efficient Viterbi scoring process and its VLSI architecture reducing dissipated power and its operation complexity…”

Section: Viterbi Scoring Proceduresmentioning

confidence: 99%