A latency optimized biased implementation style weak-indication self-timed full adder

Abstract

This article presents a biased implementation style weak-indication self-timed full adder design that is latency optimized. The proposed full adder is constructed using the delay-insensitive dual-rail code and adheres to the 4-phase handshaking. Performance comparisons of the proposed full adder vis-à-vis other strong and weakindication full adders are done on the basis of a 32-bit self-timed ripple carry adder architecture, with the full adders and ripple carry adders realized using a 32/28nm CMOS process. The results show that the proposed full adder leads to reduction in latency by 63.3% against the best of the strong-indication full adders whilst reporting decrease in area by 10.6% and featuring comparable power dissipation. On the other hand, when compared with the existing optimized weak-indication full adder, the proposed full adder is found to minimize the latency by 25.1% whilst causing an increase in area by just 1.6%, however, with no associated power penalty.

Indicating Asynchronous Multipliers

“…It can be seen from Table I that the weak-indication array multiplier incorporating the biased weak-indication full adder of [30] and the strong-indication 2-input AND function to generate the partial products enables reduced cycle time and PCTP compared to the rest with respect to RTZ and RTO handshaking. Compared to the weak-indication array multiplier embedding the weak-indication full adder of [31], the weakindication array multiplier embedding the weak-indication full adder of [30] reports corresponding reductions in cycle time and PCTP by 12.9% and 12.6% for RTZ handshaking, and by 15.5% and 15.2% for RTO handshaking respectively.…”

“…• Two indicating asynchronous array multipliers which incorporate weak-indication full adders based on [31]; corresponding to RTZ and RTO handshake protocols…”

“…It is noted that the array multiplier incorporating the weakindication full adder of [30] enables enhanced optimizations in the design metrics compared to the other indicating asynchronous array multipliers. As the size of the multiplication is increased, we hypothesize that the array multiplier utilizing the weak-indication full adder of [31] might be competitive to that utilizing the weak-indication full adder of [30]. However, higher bit-width multiplications should have to be considered to unravel the reality.…”

“…However, higher bit-width multiplications should have to be considered to unravel the reality. Nevertheless, both [30] and [31] present full adder designs which incorporate redundant logic, and it was shown in [43] that logic redundancy could help to significantly reduce the latencies and the cycle time at almost no increase in the area or average power dissipation.…”

“…The construction of indicating asynchronous array multipliers given in Table I is quite straightforward since the full adders based on the corresponding design methods [26][27][28][29][30][31] can be used to substitute the respective function blocks as shown in Fig. 3, corresponding to RTZ or RTO handshaking.…”