A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s

Senning, Christian; Bruderer, Lukas; Hunziker, Josua; Burg, Andreas

doi:10.1109/tcsi.2013.2295027

Cited by 15 publications

(4 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…TASER does not include preprocessing circuitry, whereas the Neumann-series detector [23] includes preprocessing circuitry and was optimized for wideband systems that use single-carrier frequency-division multiple access (SC-FDMA). We finally note that there exists a plethora of data-detector ASICs for traditional, small-scale MIMO systems (see [9], [10], [42], [47], [59]- [63] and the references therein). While most of these designs achieve near-ML performance and/or throughputs in the Gb/s regime in small-scale MIMO systems, their efficacy for large MIMO is unexplored-a corresponding algorithm and hardware-level comparison is left for future work.…”

Section: Asic Implementation Resultsmentioning

confidence: 99%

Data Detection in Large Multi-Antenna Wireless Systems via Approximate Semidefinite Relaxation

Castañeda

Goldstein

Studer

2016

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

Abstract-Practical data detectors for future wireless systems with hundreds of antennas at the base station must achieve high throughput and low error rate at low complexity. Since the complexity of maximum-likelihood (ML) data detection is prohibitive for such large wireless systems, approximate methods are necessary. In this paper, we propose a novel data detection algorithm referred to as Triangular Approximate SEmidefinite Relaxation (TASER), which is suitable for two application scenarios: (i) coherent data detection in large multi-user multipleinput multiple-output (MU-MIMO) wireless systems and (ii) joint channel estimation and data detection in large single-input multiple-output (SIMO) wireless systems. For both scenarios, we show that TASER achieves near-ML error-rate performance at low complexity by relaxing the associated ML-detection problems into a semidefinite program, which we solve approximately using a preconditioned forward-backward splitting procedure. Since the resulting problem is non-convex, we provide convergence guarantees for our algorithm. To demonstrate the efficacy of TASER in practice, we design a systolic architecture that enables our algorithm to achieve high throughput at low hardware complexity, and we develop reference field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) designs for various antenna configurations.Index Terms-FPGA and ASIC design, data detection, joint channel estimation and data detection, large single-input and multiple-input multiple-output (SIMO and MIMO) wireless systems, semidefinite relaxation.

show abstract

Section: Asic Implementation Resultsmentioning

confidence: 99%

Data Detection in Large Multi-Antenna Wireless Systems via Approximate Semidefinite Relaxation

Castañeda

Goldstein

Studer

2016

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…These two factors ultimately limit the efficiency of implementing SCM macros with a very wide address bus; however, our implementations show that arrays with as many as 512 rows still operate with reasonable performance, and larger memories can be achieved by multiplexing several smaller sized banks, as done with standard SRAM macros. That being said, controlled SCM implementations benefit from a wide word width and a smaller number of rows, which makes them all the more attractive for implementing memories with nonconventional wide words, such as the 17 × 230 memory banks required by the MIMO channel equalizer of Senning et al [2014] or other DSP accelerators.…”

Section: Output Multiplexer Implementationmentioning

confidence: 99%

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Teman

Rossi

Meinerzhagen

et al. 2016

ACM Trans. Des. Autom. Electron. Syst.

Self Cite

View full text Add to dashboard Cite

Embedded memory remains a major bottleneck in current integrated circuit design in terms of silicon area, power dissipation, and performance; however, static random access memories (SRAMs) are almost exclusively supplied by a small number of vendors through memory generators, targeted at rather generic design specifications. As an alternative, standard cell memories (SCMs) can be defined, synthesized, and placed and routed as an integral part of a given digital system, providing complete design flexibility, good energy efficiency, low-voltage operation, and even area efficiency for small memory blocks. Yet implementing an SCM block with a standard digital flow often fails to exploit the distinct and regular structure of such an array, leaving room for optimization. In this article, we present a design methodology for optimizing the physical implementation of SCM macros as part of the standard design flow. This methodology introduces controlled placement, leading to a structured, noncongested layout with close to 100% placement utilization, resulting in a smaller silicon footprint, reduced wire length, and lower power consumption compared to SCMs without controlled placement. This methodology is demonstrated on SCM macros of various sizes and aspect ratios in a state-of-the-art 28nm fully depleted silicon-on-insulator technology, and compared with equivalent macros designed with the noncontrolled, standard flow, as well as with foundry-supplied SRAM macros. The controlled SCMs provide an average 25% reduction in area as compared to noncontrolled implementations while achieving a smaller size than SRAM macros of up to 1Kbyte. Power and performance comparisons of controlled SCM blocks of a commonly found 256 × 32 (1 Kbyte) memory with foundry-provided SRAMs show greater than 65% and 10% reduction in read and write power, respectively, while providing faster access than their SRAM counterparts, despite being of an aspect ratio that is typically unfavorable for SCMs. In addition, the SCM blocks function correctly with a supply voltage as low as 0.3V, well below the lower limit of even the SRAM macros optimized for low-voltage operation. The controlled placement methodology is applied within a full-chip physical implementation flow of an OpenRISC-based test chip, providing more than 50% power reduction compared to equivalently sized compiled SRAMs under a benchmark application.

show abstract

“…For each MCS, the number of active receive antennas varies between N SS (the minimal number of receive antennas required for the specific MCS) and 4. In addition, all MCSs have been simulated with a hard-output lattice reduction aided linear minimum mean squared error (MMSE) MIMO detector (LRALD) [31], and a lowcomplexity soft-output MMSE detector, resulting in 112 different system modes 5 for each MIMO detector algorithm comprising Ω EG .…”

Section: Scenariosmentioning

confidence: 99%

Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems

Senning

Karakonstantis

Burg

2015

J Sign Process Syst

Self Cite

View full text Add to dashboard Cite

Energy in today's short-range wireless communication is mostly spent on the analog-and digital hardware rather than on radiated power. Hence, purely information-theoretic considerations fail to achieve the lowest energy per information bit and the optimization process must carefully consider the overall transceiver. In this paper, we propose to perform cross-layer optimization, based on an energy-aware rate adaptation scheme combined with a physical layer that is able to properly adjust its processing effort to the data rate and the channel conditions to minimize the energy consumption per information bit. This energy proportional behavior is enabled by extending the classical system modes with additional configuration parameters at the various layers. Fine grained models of the power consumption of the hardware are developed to provide awareness of the physical layer capabilities to the medium access control layer. The joint application of the proposed energy-aware rate adaptation and modifications to the physical layer of an IEEE 802.11n system, improves energy-efficiency (averaged over many noise and channel realizations) in all considered scenarios by up to 44%.

show abstract

A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s

Cited by 15 publications

References 25 publications

Data Detection in Large Multi-Antenna Wireless Systems via Approximate Semidefinite Relaxation

Data Detection in Large Multi-Antenna Wireless Systems via Approximate Semidefinite Relaxation

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems

Contact Info

Product

Resources

About