A Library for Portable and Composable Data Locality Optimizations for NUMA Systems

Majó, Zoltán; Groß, Thomas

doi:10.1145/3040222

Cited by 14 publications

(11 citation statements)

References 44 publications

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“…Most programming languages do not implement thread and data mapping algorithms that can be called from the source code [23]. Thus, the developer is required to know the implementation of the language or of the compiler to be able to map threads efficiently using specific routines [23]. The libraries that provide such routines are TBB-NUMA [23], QThreads [24] and PThreads.…”

Section: Software Libraries For Thread Mappingmentioning

confidence: 99%

“…Thus, the developer is required to know the implementation of the language or of the compiler to be able to map threads efficiently using specific routines [23]. The libraries that provide such routines are TBB-NUMA [23], QThreads [24] and PThreads. TBB-NUMA [23] is designed as a portable and composable library for parallel computation.…”

Section: Software Libraries For Thread Mappingmentioning

confidence: 99%

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Extending NUMA-BTLP Algorithm with Thread Mapping Based on a Communication Tree

Știrb

2018

Computers

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The paper presents a Non-Uniform Memory Access (NUMA)-aware compiler optimization for task-level parallel code. The optimization is based on Non-Uniform Memory Access—Balanced Task and Loop Parallelism (NUMA-BTLP) algorithm Ştirb, 2018. The algorithm gets the type of each thread in the source code based on a static analysis of the code. After assigning a type to each thread, NUMA-BTLP Ştirb, 2018 calls NUMA-BTDM mapping algorithm Ştirb, 2016 which uses PThreads routine pthread_setaffinity_np to set the CPU affinities of the threads (i.e., thread-to-core associations) based on their type. The algorithms perform an improve thread mapping for NUMA systems by mapping threads that share data on the same core(s), allowing fast access to L1 cache data. The paper proves that PThreads based task-level parallel code which is optimized by NUMA-BTLP Ştirb, 2018 and NUMA-BTDM Ştirb, 2016 at compile-time, is running time and energy efficiently on NUMA systems. The results show that the energy is optimized with up to 5% at the same execution time for one of the tested real benchmarks and up to 15% for another benchmark running in infinite loop. The algorithms can be used on real-time control systems such as client/server based applications which require efficient access to shared resources. Most often, task parallelism is used in the implementation of the server and loop parallelism is used for the client.

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Section: Software Libraries For Thread Mappingmentioning

confidence: 99%

Section: Software Libraries For Thread Mappingmentioning

confidence: 99%

Extending NUMA-BTLP Algorithm with Thread Mapping Based on a Communication Tree

Știrb

2018

Computers

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“…As corroborated by a large amount of work in operating systems [12,14,18,19,35,61,70,74], databases [36,44,62,63,75], programming languages [37,58], parallel runtimes [7,9,41,52], key-value stores [15,51], and synchronization [22-24, 32, 45], system developers need to optimize software for the target platform to achieve good performance. We discuss below selected examples of multi-core optimizations.…”

Section: Related Workmentioning

confidence: 99%

Abstracting Multi-Core Topologies with MCTOP

Chatzopoulos

Guerraoui

Harris

et al. 2017

Proceedings of the Twelfth European Conference on Computer Systems

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Portability and efficiency are usually antagonists in multicore computing. In order to develop efficient code, one needs to take into account the topology of the target multi-cores (e.g., for locality). This clearly hampers code portability. In this paper, we show that you can have the cake and eat it too.We introduce MCTOP, an abstraction of multi-core topologies augmented with important low-level hardware information, such as memory bandwidths and communication latencies. We show how to automatically generate MCTOP using libmctop, our library that leverages the determinism of cache-coherence protocols to infer the topology of multi-cores using only latency measurements.MCTOP enables developers to accurately and portably define high-level performance optimization policies. We illustrate several such policies through four examples: (i-ii) thread placement in OpenMP and in a MapReduce library, (iii) a topology-aware mergesort algorithm, as well as (iv) automatic backoff schemes for locks. We illustrate the portability of these optimizations on five processors from Intel, AMD, and Oracle, with low effort.

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“…Starting with userland methods, it is possible to statically place arrays and computations to bring NUMA awareness to OpenMP programs [27,2,34,32] or applications using TBB [26]. Such approaches are well suited to regular data structures and involve target-specific optimizations by the programmer.…”

Section: Related Workmentioning

confidence: 99%

“…On the operating system side, optimizations are compelled to place tasks and data conservatively [13,24], unless provided with detailed affinity information by the application [5,6], high-level libraries [26] or domain specific languages [20]. Nevertheless, as task-parallel run-times operate in user-space, a separate kernel component would add additional complexity to the solution; this advocates for a user-space approach.…”

Section: Introductionmentioning

confidence: 99%

Scalable Task Parallelism for NUMA

Drebes

Pop

Heydemann

et al. 2016

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation

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Dynamic task-parallel programming models are popular on shared-memory systems, promising enhanced scalability, load balancing and locality. These promises, however, are undermined by non-uniform memory access (NUMA). We show that using NUMA-aware task and data placement, it is possible to preserve the uniform hardware abstraction of contemporary task-parallel programming models for both computing and memory resources with high data locality. Our data placement scheme guarantees that all accesses to task output data target the local memory of the accessing core. The complementary task placement heuristic improves the locality of accesses to task input data on a best effort basis. Our algorithms take advantage of data-flow style task parallelism, where the privatization of task data enhances scalability by eliminating false dependences and enabling fine-grained dynamic control over data placement. The algorithms are fully automatic, application-independent, performance-portable across NUMA machines, and adapt to dynamic changes. Placement decisions use information about inter-task data dependences readily available in the run-time system, and placement information from the operating system. On a 192-core system with 24 NUMA nodes, our optimizations achieve above 94% locality (fraction of local memory accesses), up to 5× better performance than NUMAaware hierarchical work-stealing, and even 5.6× compared to static interleaved allocation. Finally, we show that stateof-the-art dynamic page migration by the operating system cannot catch up with frequent affinity changes between cores and data and thus fails to accelerate task-parallel applications.

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A Library for Portable and Composable Data Locality Optimizations for NUMA Systems

Cited by 14 publications

References 44 publications

Extending NUMA-BTLP Algorithm with Thread Mapping Based on a Communication Tree

Extending NUMA-BTLP Algorithm with Thread Mapping Based on a Communication Tree

Abstracting Multi-Core Topologies with MCTOP

Scalable Task Parallelism for NUMA

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