A local reconfiguration based scalable fault tolerant many-processor array

Banerjee, Soumya; Rao, Wenjing

doi:10.1109/aspdac.2017.7858361

Cited by 2 publications

(2 citation statements)

References 24 publications

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“…Techniques based on redundancy are widely used in fault tolerance; Such as N-tuple modular redundancy (e.g. TMR), 3,4 reconfiguration, 5,6 quadded logic, 7 interwoven redundancy logic, 8 etc. 9,10 However, in nanocomputers, since the faulty components are ubiquitous in space and time, it is hard to achieve high fault tolerance with these techniques alone.…”

Section: R E T R a C T E Dmentioning

confidence: 99%

RETRACTED: Redundancy-modified NAND multiplexing for nanocomputers

Diao

Chen

2020

International Journal of Electrical Engineering & Education

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It is necessary to study fault tolerant techniques for nanotechnology since nanometer devices are very sensitive to system and environment influences. In this paper, we present a novel fault tolerant technique for nanocomputers, namely, XOR multiplexing based on redundancy-modified NAND gates. The error distributions and fault tolerant ability of the proposed architecture are analyzed and compared them with von Neumann’s multiplexing. Experimental results show that compared with conventional multiplexing technique based on NAND gate, the new system has a much higher fault tolerant ability. According to the evaluation, by using multiple redundant components, the device error tolerant ability of the proposed architecture can up to the 10−1. In unreliable nanometer-scale devices-based systems, this architecture is potentially effective against the increasing transient errors.

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Section: R E T R a C T E Dmentioning

confidence: 99%

RETRACTED: Redundancy-modified NAND multiplexing for nanocomputers

Diao

Chen

2020

International Journal of Electrical Engineering & Education

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“…Hence, how to build reliable systems out of unreliable components is an inevitable problem. In order to solve this problem, scholars have investigated several redundant fault-tolerant techniques, such as N-tuple modular redundancy (e.g., triple modular redundancy) [9,10] and reconfiguration [11][12][13]. However, these techniques do not yield high fault tolerance for nanocomputers due to the extreme high devices' density and the high percentage of faulty components.…”

Section: Introductionmentioning

confidence: 99%

XOR Multiplexing Technique for Nanocomputers

Diao

Chen

et al. 2020

Applied Sciences

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In emerging nanotechnologies, due to the manufacturing process, a significant percentage of components may be faulty. In order to make systems based on unreliable nano-scale components reliable, it is necessary to design fault-tolerant architectures. This paper presents a novel fault-tolerant technique for nanocomputers, namely the XOR multiplexing technique. This hardware redundancy technique is based on a numerous duplication of faulty components. We analyze the error distributions of the XOR multiplexing unit and the error distributions of multiple stages of the XOR multiplexing system, then compare them to the NAND multiplexing unit and the NAND multiplexing multiple stages system, respectively. The simulation results show that XOR multiplexing is more reliable than NAND multiplexing. Bifurcation theory is used to analyze the fault-tolerant ability of the system and the results show that XOR multiplexing technique has a high fault-tolerant ability. Similarly to the NAND multiplexing technique, this fault-tolerant technique is a potentially effective fault tolerant technique for future nanoelectronics.

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A local reconfiguration based scalable fault tolerant many-processor array

Cited by 2 publications

References 24 publications

RETRACTED: Redundancy-modified NAND multiplexing for nanocomputers

RETRACTED: Redundancy-modified NAND multiplexing for nanocomputers

XOR Multiplexing Technique for Nanocomputers

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