A Lock-Time Improvement for an X-Band Frequency Synthesizer Using an Active Fast-Lock Loop Filter

Abstract

In phase-locked frequency synthesizers, a fast-lock technique is frequently employed to overcome the trade-off between a lock-time and a spurious response. The function of fast-lock in a conventional PLL (Phased Lock Loop) IC (Integrated Circuit) is limited by a factor of 16, which is usually implemented by a scaling of charge pumper, and consequently a lock time improvement of a factor of 4 is possible using the conventional PLL IC. In this paper, we propose a novel external active fast-lock loop filter. The proposed loop filter provides, conceptually, an unlimited scaling of charge pumper current, and can overcome conventional trade-off between lock-time and spur suppression. To demonstrate the validity of our proposed loop-filter, we fabricated an X-band frequency synthesizer using the proposed loop filter. The loop filter in the synthesizer is designed to have a loop bandwidth of 100 kHz in the fast-lock mode and a loop bandwidth of 5 kHz in the normal mode, which corresponds to a charge pumper current change ratio of 400. The X-band synthesizer shows successful performance of a lock-time of below 10 μsec and reference spur suppression below -64 dBc. Ⅰ. IntroductionA frequency synthesizer is frequently used as a signal source, and is regarded as an essential device in communication systems. Its frequency can be synthesized using the control signals from a program in a personal computer. Various implementations for frequency synthesizers are proposed [1]. One of them is using PLL (Phase Locked Loop), which is based on frequency divider. Fig. 1 shows a typical block diagram of our frequency synthesizer using frequency dividers. In comparison to a conventional frequency synthesizer, a divider of 1/4 is internally built in a voltage controlled oscillator (VCO) IC. In Fig. 1, a desired where N is division ratio of VCO frequency. Thus, the frequency of VCO can be synthesized with a step frequency CH f by changing the value of N. The important figures of merit in this type of frequency synthesizer are lock-time and reference spur suppression, which are critically dependent on the loop filter bandwidth. As a loop bandwidth increases, lock-time is decreased but spurs increase. Conversely, when a loop bandwidth decreases, spurs are suppressed but lock-time increases.Such trade-off makes it difficult to implement the loop filter to yield both a satisfactory fast lock-time and spur suppression. However, recent communication and military applications require more stringent spectral purity of signal sources, with faster settling time.To address this trade-off between settling time and loop bandwidth, several works were introduced [2]～ [6]. One design approach is to utilize a pre-determined lookup table to adjust the output frequency immediately [5], [6]. The lookup table initially records the proper frequency-setting configurations for all channels. When the PLL is commanded to change its frequency to a certain