A look underneath the SiO₂/4H-SiC interface after N₂O thermal treatments

Abstract

SummaryThe electrical compensation effect of the nitrogen incorporation at the SiO2/4H-SiC (p-type) interface after thermal treatments in ambient N2O is investigated employing both scanning spreading resistance microscopy (SSRM) and scanning capacitance microscopy (SCM). SSRM measurements on p-type 4H-SiC areas selectively exposed to N2O at 1150 °C showed an increased resistance compared to the unexposed ones; this indicates the incorporation of electrically active nitrogen-related donors, which compensate the p-type doping in the SiC surface region. Cross-sectional SCM measurements on SiO2/4H-SiC metal/oxide/semiconductor (MOS) devices highlighted different active carrier concentration profiles in the first 10 nm underneath the insulator–substrate interface depending on the SiO2/4H-SiC roughness.The electrically active incorporated nitrogen produces both a compensation of the acceptors in the substrate and a reduction of the interface state density (D it). This result can be correlated with the 4H-SiC surface configuration. In particular, lower D it values were obtained for a SiO2/SiC interface on faceted SiC than on planar SiC. These effects were explained in terms of the different surface configuration in faceted SiC that enables the simultaneous exposition at the interface of atomic planes with different orientations.

Characterization of SiO2/4H-SiC Interfaces in 4H-SiC MOSFETs: A Review

“…This effect has been quantified by Fiorenza et al [51], by means of cross sectional scanning capacitance microscopy (SCM) measurements on the SiO 2 /4H-SiC interface. In particular, SCM in cross sections showed that the faceted 4H-SiC surface morphology incorporates a larger nitrogen amount compared to the basal planes, because it exposes different ratios between (0001) and (11−20) planes [47]. Other studies based on transmission electron microscopy (TEM) [52,53] and X-ray photoemission spectroscopy (XPS) [49] demonstrated that nitrogen is incorporated within a couple of 4H-SiC crystalline monolayers.…”

“…Fabrication details can be found in Reference [55]. As can be seen, the number of free carriers in the nitridated sample is increased by more than one order of magnitude in a region about 10 nm wide from the SiO2/4H-SiC interface [47,51]. Thus, it can be concluded that the nitridation process modifies only a small fraction of the 4H-SiC crystal (one-two monolayers) but it increases the free carrier concentration in the MOSFET inversion region, effectively reducing the channel resistivity.…”

“…The non-uniform spatial distribution of the capacitance signal can be associated with the spatial fluctuation of the surface potential. For example, in a faceted surface, the non-uniform D it spatial distribution is correlated with[46] the different contributions to the total D it value given by the (11−2n) planes of the surface facets and the (0001) basal planes[47]. Saitoh et al[48] reported on the variation in the density of the interface states in MOS capacitors fabricated on 4H-SiC with different miscut angles, moving from 8 • , i.e., the (0001) largest basal plane, up to 90 • toward the[11−20] direction, i.e., the(11−20) plane.Energies 2019, 12, 2310 10 of 22 Energies 2019, 12, x FOR PEER REVIEW 10 of 22…”

High-Resolution Two-Dimensional Imaging of the 4H-SiC MOSFET Channel by Scanning Capacitance Microscopy

“…In recent years, two-dimensional (2D) carrier profiling techniques based on atomic force microscopy, such as scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM), have been also explored to evaluate the electrically active profiles in ion-implanted 4H-SiC [ 14 ]. In particular, the SCM technique, based on local differential capacitance (dC/dV) measurements with a sliding metal tip, is very powerful for the delineation of the electrical junction position in semiconductor devices, by exploiting the sensitivity to the doping type of the dC/dV phase signal [ 15 ].…”

The influence of SiC/SiO<inf>2</inf> interface morphology on the electrical characteristics of SiC MOS structures

“…Although many methods have been adopted to improve the surface roughness, such as using a protective layer of a graphitic cap, there still exists controversy about the influence of SiC/SiO 2 interface morphology after the postimplantation annealing on the interface state density and channel mobility. Fiorenza [3] , recently reported that the carbon cap used to protect SiC surface during 1650 C high temperature annealing results in an increased interface state density (D it ) and a decreased channel mobility compared to the devices without carbon cap. They attributed the increased D it to the different areal percentage exposing different basal planes before and after carbonization [4] .…”