A low complexity bit parallel polynomial basis systolic multiplier for general irreducible polynomials and trinomials

Devi, Sakshi; Mahajan, Rita; Bagai, Deepak

doi:10.1016/j.mejo.2021.105163

Cited by 4 publications

(2 citation statements)

References 27 publications

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“…These includes (i) bit-serial, (ii) bit-parallel, (iii) digit-serial and (iv) digit-parallel approaches. Moreover, some systolic polynomial multiplication designs are also described in [33][34][35]. In this context, the bit-serial designs are more appropriate for achieving the low-area and power-efficient architectures.…”

Section: Arithmetic and Logic Unit (Alu)mentioning

confidence: 99%

A Coprocessor Architecture for 80/112-bit Security Related Applications

Rashid¹,

Alotaibi²

2023

Computers, Materials &Amp; Continua

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We have proposed a flexible coprocessor key-authentication architecture for 80/112-bit security-related applications over GF (2 m ) field by employing Elliptic-curve Diffie Hellman (ECDH) protocol. Towards flexibility, a serial input/output interface is used to load/produce secret, public, and shared keys sequentially. Moreover, to reduce the hardware resources and to achieve a reasonable time for cryptographic computations, we have proposed a finite field digit-serial multiplier architecture using combined shift and accumulate techniques. Furthermore, two finite-statemachine controllers are used to perform efficient control functionalities. The proposed coprocessor architecture over GF 2 163 and GF 2 233 is programmed using Verilog and then implemented on Xilinx Virtex-7 FPGA (field-programmable-gate-array) device. For GF 2 163 and GF 2 233 , the proposed flexible coprocessor use 1351 and 1789 slices, the achieved clock frequency is 250 and 235 MHz, time for one public key computation is 40.50 and 79.20 μs and time for one shared key generation is 81.00 and 158.40 μs. Similarly, the consumed power over GF 2 163 and GF 2 233 is 0.91 and 1.37 mW , respectively. The proposed coprocessor architecture outperforms state-of-the-art ECDH designs in terms of hardware resources.

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Section: Arithmetic and Logic Unit (Alu)mentioning

confidence: 99%

A Coprocessor Architecture for 80/112-bit Security Related Applications

Rashid¹,

Alotaibi²

2023

Computers, Materials &Amp; Continua

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“…Modern cryptography requires a search for more efficient calculation methods to improve the performance of the final encryption device [1][2][3][4][5]. A high-speed device for encrypting and decrypting data can be built on the basis of non-positional polynomial number systems (NPNS).…”

Section: Introductionmentioning

confidence: 99%

Development of pipelined polynomial multiplier modulo irreducible polynomials for cryptosystems

Tynymbayev

Ibraimov

Namazbayev

et al. 2022

EEJET

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In this paper, we consider a schematic solution of the pipeline multiplier modulo, where multiplication begins with the analysis of the lowest order of the polynomial multiplier, which can serve as an operating unit for high-speed encryption and decryption of data by hardware implementation of cryptosystems based on a non-positional polynomial notation. The functional diagram of the pipeline and the structure of its logical blocks, as well as an example of performing the operation of multiplying polynomials modulo, are given. The correct functioning of the developed circuit was checked by modeling in the Vivado Design Suite computer-aided design for the implementation of the multiplication device on the development/evaluation kit Artix-7 based on the Spartan 6 field-programmable gate array series by Xilinx. The effectiveness of the proposed hardware pipeline multiplier in modulo is confirmed by the Verilog Testbench timing diagram implemented for the evaluation kit Artix-7 field-programmable gate array. In addition, the developed pipelined modulo multiplier takes no more than 0.02 % of the resources of the used field-programmable gate array for a given length of input data. Compared to the matrix multiplication method, a pipelined modulo multiplier can handle a large data stream without waiting for the result of the previous multiplication step. The modulo pipelined multiplier depth depends on the bit width of the input data. The developed pipeline device can be used in digital computing devices operating in a polynomial system of residue classes, as well as for high-speed data encryption in blocks of cipher processors operating on the basis of a non-positional polynomial number system.

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Parallel Modular Multiplication Using Variable Length Algorithms

Mirzaei-Teshnizi,

Keshavarzi

2025

IEEE Trans. Comput.

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A low complexity bit parallel polynomial basis systolic multiplier for general irreducible polynomials and trinomials

Cited by 4 publications

References 27 publications

A Coprocessor Architecture for 80/112-bit Security Related Applications

A Coprocessor Architecture for 80/112-bit Security Related Applications

Development of pipelined polynomial multiplier modulo irreducible polynomials for cryptosystems

Parallel Modular Multiplication Using Variable Length Algorithms

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