2011 IEEE 15th International Symposium on Consumer Electronics (ISCE) 2011
DOI: 10.1109/isce.2011.5973878
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A low-complexity, hardware architecture for a parametric, real-time, LSF speech decoder

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“…The LSF-to LPC conversion algorithm was implemented in hardware, alongside with the LPC synthesis filter, on Virtex 5 FPGA platform. The hardware architecture has been described in [6]. Other algorithms and scripts shown in fig.…”
Section: E Ncoder Decodermentioning
confidence: 99%
“…The LSF-to LPC conversion algorithm was implemented in hardware, alongside with the LPC synthesis filter, on Virtex 5 FPGA platform. The hardware architecture has been described in [6]. Other algorithms and scripts shown in fig.…”
Section: E Ncoder Decodermentioning
confidence: 99%