A low-complexity, reduced-power Viterbi Algorithm

Abstract

We present two memory-, process-and powerefficient algorithmic transformations for the Viterbi Algorithm (VA). The first performs in-place computations reducing memory required and bit transitions on the data address bus, while the second simplifies the traceback routine of the VA.

Research on equalization based on MLSE

“…The highest probability path through the trellis identifies the received bit pattern. In order to compensate for PMD, the length of the trellis should be close to the duration of the dispersed pulse [5].The MLSE trellis size increases exponentially with the number of taps implemented.…”

“…More specifically, the maximum likelihood sequence solution is to "choose" that sequence of symbols that maximizes the likelihood of the received sequence of observations. The obtained sequence is optimal and the procedure is referred to as maximum likelihood sequence estimation (MLSE).Here the MLSE equalizer is implemented by Viterbi algorithm [5] . The…”

Low Complexity Radix-4 Butterfly Design for the Viterbi Decoder

“…In the last few years, several articles [5]- [7] have been devoted to use the branch symmetry to reduce the computing complexity of the Viterbi decoder. Unfortunately, the branch symmetry only works for the Viterbi decoder with radix-2 butterfly.…”

“…In order to reduce the computational complexity, the radix-2 butterfly is applied to the implementation of the Viterbi decoder [5]- [7]. The butterfly contains a pair of origin and destination states, and four branches.…”

Autonomous system clock frequency controller for pico- and nano- satellites

“…Moreover, there were also some research works aimed to reduce the use of energy in various aspects of the satellite such as its flying region [31], communication link [32], as well as computational algorithm [33,34].…”