A Low Cost 100 MHz 2-Stage PSiP and Evolution to a Co-Packaged/Fully-Integrated Voltage Regulator for SoC Power Delivery

Doyle, J.; Stiff, Jonathon C.; Kulkarni, Santosh; Yıldız, Aysel

doi:10.1109/cicc.2019.8780244

Cited by 4 publications

(8 citation statements)

References 17 publications

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“…Similar to Section II-A, ω 0 calculations assume the gain of the highest order of the filter transfer function in (12) for nth harmonic as follows:…”

Section: B 4thres Low-pass Filtermentioning

confidence: 99%

“…The considered converter steady-state specifications for this study are listed in Table I, which are typical of point-of-load converter requirements for an intermediate step-down stage, which then is followed by a second stage with tighter output voltage regulation as shown in [1], [12], and [16] for IVR application. The basic buck converter second-order output filter in Fig.…”

Section: Design Studymentioning

confidence: 99%

“…The comparison is demonstrated for air-core printed circuit board (PCB) integrated inductors, where the target application is the first stage of a 2-stage step-down solution for integrated voltage regulator (IVR) type loads powered by a wide input voltage battery source, e.g., as in [12], where stages 1 and 2 step down battery voltage from 3.8 to 1.5 V and then from 1.5 to 1 V, respectively. This article is an extension of our previous conference paper [13], where new s-domain and time-domain analyzes are presented to predict the voltages and currents in the filter components.…”

mentioning

confidence: 99%

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Design Procedure for Reduced Filter Size in a Buck Converter Using a Fourth-Order Resonance Filter

Kandeel¹,

O’Driscoll

O’Mathuna

et al. 2023

IEEE Trans. Power Electron.

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This article presents a novel design procedure for fourth order and fourth-order resonance (4thRes) output filters, for given buck converter specifications, making components selection a straightforward process. An accurate filter analysis is provided to predict the filter component currents and voltages in both frequency and time domains. Application of the analysis in a design study of a 20 MHz, 5.4 W buck converter shows that the 4thRes filter has the potential to reduce the output passive components for a wide duty cycle range. As compared with a second-order filter at V IN = 6.6 V to V OUT = 1.8 V, total inductance, inductor energy, capacitance, and capacitor energy are 58%, 35%, 45%, and 31% lower, respectively. Air-core printed circuit board (PCB) integrated solenoid inductors are considered for implementation and testing within a prototype converter to show the impact of these filters on the converter performance. The 4thRes filter achieved 3.7% and 3.6% higher full-load efficiency than the second-and fourth-order filters, respectively, and a better load transient performance.

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“…Similar to Section II-A, ω 0 calculations assume the gain of the highest order of the filter transfer function in (12) for nth harmonic as follows:…”

Section: B 4thres Low-pass Filtermentioning

confidence: 99%

Section: Design Studymentioning

confidence: 99%

mentioning

confidence: 99%

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Design Procedure for Reduced Filter Size in a Buck Converter Using a Fourth-Order Resonance Filter

Kandeel¹,

O’Driscoll

O’Mathuna

et al. 2023

IEEE Trans. Power Electron.

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show abstract

“…This miniaturizes switches and inductors that primarily dominate the system size and weight. As a result, the integration level has evolved into a 3D stacked power supply (3D-SPS, discrete switch and discrete inductor), power supply in package (PSiP, integrated switch and discrete inductor), and power supply on chip (PwrSoC, integrated switch and integrated inductor) [5][6][7]. These integration levels differentiate in switching frequency and power rate and applications, as shown in Table 1.…”

Section: Introductionmentioning

confidence: 99%

Technical Reviews of Power Loss Optimization in High-Frequency PSiPs—In Relation to Power Switches and Power Inductors

Wang,

Zhang,

et al. 2023

Applied Sciences

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Power losses of switches and inductors are consistent challenges that hinder the development of high-frequency power supply in package (PSiP). This paper investigates the roadmap for power loss optimizations of switches and inductors in high-frequency PSiPs. Firstly, a size and parallel quantity design method to reduce power loss in an integrated Si LDMOSFET is provided with comprehensive consideration of switching frequency and power levels. Secondly, quality factors of different air-core inductors are analyzed with consideration of geometric parameters and skin effect, which provides the winding structure optimization to reduce power losses. The power losses of the integrated Si LDMOSFET and air-core inductors are both reduced to less than 10% of the output power at 1~100 MHz switching frequency and 0.1~10 W power level. Finally, based on the above optimizations, power losses of switches and inductors are calculated with switching frequency and power level. Combining the calculated results, this paper predicts the efficiency boundaries of PSiPs. Upon efficiency normalization with consideration of input and output voltage levels, all the predictions are consistent with the published literature. The efficiency predication error is 1~15% at 1~100 MHz switching frequency and 0.1~10 W power level. The above power loss optimizations improve the efficiency, which provides potential roadmaps for achieving high-frequency PSiPs.

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“…Determining the number of phases for optimized overall inductor density is essential, especially for size-sensitive applications such as converters employing on-chip and copackaged inductors, as in [5] (1-4 phases), [6] (1-8 phases), [7] (1-4 phases), and [8] (16 phases). The interleaved buck has been widely investigated for various converter specifications and packaging technologies, e.g., [9], [10], [11], [12], [13], [14].…”

mentioning

confidence: 99%

Optimum Phase Count in a 5.4-W Multiphase Buck Converter Based on Output Filter Component Energies

Kandeel

O’Driscoll

O’Mathuna

et al. 2023

IEEE Trans. Power Electron.

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This article presents an analysis of low-power, multiphase interleaved buck converters to illustrate the extent to which adding more phases is beneficial for reducing the passive components' sizes. The analysis focuses on a typical converter application with a wide operating duty cycle range and requires good load transient. It is shown that by restricting the phase current ripple, the theoretical reduction in total inductor peak energy predicted for increased phase numbers is limited. The article assesses the benefit of inductor coupling and presents guidelines for coupling factor selection to avoid steady-state inductance roll-off over the wide input voltage range. Standard printed circuit board (PCB) manufacturing design rules are shown to place a practical phase count limit considering the reduction in total inductor size. PCB integrated, air-core solenoid and spiral inductors are implemented in both single-and two-phase 5.4 W, 20 MHz buck converter prototypes. When compared with single-phase designs, two-phase spiral inductors are 44% smaller, and the two-phase solenoid has a 54% lower loss. The two-phase prototype converter achieves better overall efficiency and peaks at almost 90% at V IN = 4.5 V, V OUT = 1.8 V, and F SW = 20 MHz.

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A Low Cost 100 MHz 2-Stage PSiP and Evolution to a Co-Packaged/Fully-Integrated Voltage Regulator for SoC Power Delivery

Cited by 4 publications

References 17 publications

Design Procedure for Reduced Filter Size in a Buck Converter Using a Fourth-Order Resonance Filter

Design Procedure for Reduced Filter Size in a Buck Converter Using a Fourth-Order Resonance Filter

Technical Reviews of Power Loss Optimization in High-Frequency PSiPs—In Relation to Power Switches and Power Inductors

Optimum Phase Count in a 5.4-W Multiphase Buck Converter Based on Output Filter Component Energies

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