A Low-Cost Design of 2D Median Filter

Abstract

The median filter plays an important role in image processing for noise removing. To enhance the operating speed, hardware implementation of median filter on field programmable gate arrays (FPGA) or application specific IC (ASIC) are necessary and inevitable. This paper presents a low-cost and high-throughput hardware design for two-dimensional (2D) median filter. Two techniques are employed to reduce circuit area. One is the parallel three-valued sorting method for reducing the number of pipelined registers under constant speed, and the other is the functional sharing method used to implement median value sorting with the least number of comparisons. The proposed 2D median filter is implemented by two different synthesized methods. One is synthesized by Synopsys Design Compiler with the TSMC 90nm cell library (ASIC design) and the other is synthesized by Xilinx FPGA Virtex7 XC7VX690T (FPGA design). Experimental results show that the area cost of the proposed design is reduced more than 30% on average in comparison to the previous designs.INDEX TERMS Hardware implementation, low-cost, two-dimensional (2D), median filter.

Automated breast cancer detection system from breast mammogram using deep neural network

“…This process does not change the features of the original image it only enhances the features. The pre-processing uses 2D median image filter function that increases the mammography image quality by clearing and fading the unwanted image portions out of sight and makes the image suitable for further processing [17], [18]. The mechanism of this filter is it moves every pixel one by one and then every pixel value is altered by the median of neighbouring pixel value.…”

Area Efficient Parallel Median Filter Using Approximate Comparator and Faithful Adder

“…Note from Fig. 8b, the maximal delay of the proposed adder for n bits in input operands and m = 4 is given by t logic − depth = 1 * t AND + 2 * t NAND + 2 * t OR + 2 * t XOR +1 * t BEC + n/2m * t MUX (17) and it increases by O(n/2m*t MUX ) . Though we use look-ahead based approach for carry generation within the block, it does not and carry output C out .…”

“…Approximate adders and multipliers for digital image processing are proposed in [9][10][11][12][13][14][15]. Median filters that use regular sorting and two-dimensional rank order based sorting are proposed in [16][17][18]. An adaptive window and the fuzzy logic-based median filter are proposed in [19].…”

VLSI Implementation of LFA based Median Filter with Noise Detection Architecture for EMG Denoising

“…Hsiao, and S.H. Lin [15] developed a low cost and high throughput design for two dimensional (2D) hardware design. Parallel three value sorting methods and the functional sharing method were used to reduce the size of the circuit area.…”

“…The comparative results of conventional method with proposed method is presented in Table 7. In this table, ENLMS [12], LLMF [14] and LCMF [15] methods takes more FPGA performances compared to the LFA-MF. From this table, it is clear that LFA-MF method performed effectively with less hardware utilization.…”