A Low-Cost Low-Power CMOS Time-to-Digital Converter Based on Pulse Stretching

Yang

IEICE Electron. Express

et al. 2014

A successive approximation time-to-digital converter (TDC) is presented. The proposed TDC is based on the vernier charging method, and characterized with its timing resolution independent of the period of the reference clock. Further by including voltage ratio together with both current and capacitor ratios to enlarge the pulse stretch factor, a higher timing resolution is attained. The circuit is implemented in a 130 nm CMOS process and occupies an area of 0.32×0.21 mm 2 . According to the simulation results, the proposed TDC achieves typically 6.25 ps resolution and consumes 0.9 mW from a 1.5 V supply voltage.

Section: Circuit Implementation and Simulation Resultsmentioning

confidence: 99%

“…Dual-slope [2,3] and triple-slope [4] methods are developed in analogue TDCs to quantize the time interval. In [2,3,4], the input pulses are firstly stretched by utilizing the capacitor or current (resistor) ratio. Then a counter keeps track of full clock cycles in the stretched pulse.…”

Section: Introductionmentioning

confidence: 99%

Successive approximation time-to-digital converter based on vernier charging method

Yang

IEICE Electron. Express

et al. 2014

“…The delay time of the two delay lines are controlled by the voltage provided by the Dual-DLL. According to the delay time determined above, fine quantization resolution is: (3) In this paper, the reference clock is 125MHZ and n is 32, . The dynamic range of fine stage is , which matches the resolution of middle stage.…”

Section: Vdl Architecturementioning

confidence: 99%

“…Traditional analog approaches use time amplifier(TA) [2] or time to voltage converter(TVC) [3]to achieve high resolution, but these methods are area-consuming and with, higher cost, lower conversion rate and higher power supply comparing with digital approaches. As for digital TDC, high resolution is achieved by using the gate delay of the delay cell as TDC's quantization step.…”

Section: Introductionmentioning

confidence: 99%

A Coarse-Fine Time-to-Digital Converter

2017

Abstract.A design of time-to-digital converter (TDC) using a coarse-fine conversion scheme is presented. The coarse stage was accomplished by a delay line, and used a loop counter at the end of the delay line to achieve wide dynamic range. The fine stage utilized the dual DLL structure to achieve high precision. The proposed TDC can provide high resolution with less chip area. With an input reference clock of 125MHZ, the TDC achieves 8ps resolution, and the dynamic range achieves 1.5µs.

Analog Integr Circ Sig Process

“…The circuit in Figure 2-13 is just one of the many TDC designs that have been proposed. Many different styles exist, such as those described in [17], [18] and [19].…”

Section: Time-to-digital Convertermentioning

confidence: 99%

Sampled-data IIR filtering via time-mode signal processing

Guttman

Roberts

2011

ACKNOWLEDGMENTSFirst, I would like to thank my supervisor, Professor Gordon Roberts, for giving me the opportunity to study in his research group. I would not have been able to complete this thesis without his guidance, his enthusiasm, and his dedication.He has always been able and available to offer me both professional and academic advice, for which I will always be grateful. To Dong ( -ii - ABSTRACTIn this work, the design of sampled-data infinite impulse response filters based on time-mode signal processing circuits is presented. Time-mode signal processing (TMSP), defined as the processing of sampled analog information using timedifference variables, has become one of the more popular emerging technologies in circuit design. As TMSP is still relatively new, there is still much development needed to extend the technology into a general signal-processing tool. In this work, a set of general building block will be introduced that perform the most basic mathematical operations in the time-mode. By arranging these basic structures, higher-order timemode systems, specifically, time-mode filters, will be realized. Three second-order time-mode filters (low-pass, band-reject, high-pass) are modeled using MATLAB, and simulated in Spectre to verify the design methodology. Finally, a damped integrator and a second-order low-pass time-mode IIR filter are both implemented using discrete components.-iii -