A low-cost programmable clock generator for switched-capacitor circuit applications

Abstract

This paper presents two improved circuit techniques that allow the design of a low-cost programmable clock generator using a ring oscillator for low-frequency switched-capacitor applications. The first technique aims at reducing the frequency of the oscillator with small capacitors by proposing a Miller current-starved inverter ring oscillator.For identical values of integrated components in implementation, the proposed ring oscillator reduces the oscillation frequency by 5 times over the conventional ring oscillator and 3 times over the conventional current-starved inverter ring oscillator. This benefits the relaxation of PSRR requirement and the reduction of substrate noise coupling in mixed-signal circuits. The second technique aims at enhancing the reliability of the programmed data by proposing orthogonal fusible link trimming circuit. The experimental results have verified that the programming range of 56 kHz to 1.042 MHz is achieved using discrete-step tuning on small capacitor values from 0.375 pF to 5.625 pF together with frequency division by four divider stages, whilst the jitter is less than 300 ps at ± 10% variation in a 5 V supply in the entire tuning range.

A high PSR voltage reference for DC-to-DC converter applications

“…However, mismatch of components will reduce the accuracy of the voltage reference, but it can be compensated by trimming the gain network in the difference amplifier. For instance, it can be realized by poly fuse trimming method [8]. It is mainly because calibration is the usual procedure for manufacture.…”

Low Frequency Ring Oscillator and Its Use in Non Overlapping Clock Generation

“…The delay of the proposed inverter cell is the sum of the delay offered by the pass gate and that of the degraded input CMOS inverter. Thus, the low-to-high and high-to-low delay of the proposed inverter cell is given by: τ pLH (tot) = τ p (pmos) + τ pLH (inv) (6) τ pHL (tot) = τ p (pmos) + τ pHL (inv) (7) It should be noted that apart from the fact that PMOS pass gate increases the delay of the inverter, the delay of the CMOS inverter itself increases due to the degraded signal swing. For simplicity, we have considered that |V Tp | = V Tn .…”

“…If the circuits given in Fig. 6 are used, then (8) must be added to (7) and (6). Also, it should be noted that since the input to the inverter will now swing between |V Tp | and V DD − V Tn , the expression for the propagation delay of the inverter has to be modified accordingly.…”

“…Nonoverlapping clock generator is one of the key building blocks of an SC circuit. Numerous techniques for clock generation are proposed in [6]- [9].…”

A Capacitive-Based Accelerometer IC Using Injection-Nulling Switch Technique

“…7. The ASIC comprises a sense amplifier, a gain stage, a filter stage, an output stage, an oscillator [23], a clock generator [23], a trimming and control logic circuit [23], and a serial-to-parallel register [23]. The self-test and the filter bandwidth are controlled by respective external inputs.…”